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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-10-16 13:35:04 +0300 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-18 12:31:15 +0000 |
commit | 5791123356c7edd2942f87f5ba2786143776fe54 (patch) | |
tree | 7fc7a076ea6da2169764cb67224c77340ec34648 /util/riscv/spike-elf.ld | |
parent | a000922e077ec906c39c5e07ba2e38feefd5b8c0 (diff) |
cpu/intel/hyperthreading: Use initial LAPIC IDs
For older CPU models where CPUID leaf 0xb is not supported, use
initial LAPIC ID from CPUID instead of LAPIC register space to
to detect if logical CPU is a hyperthreading sibling. The one
in LAPIC space is more complex to read, and might not reflect
CPU topology as it can be modified in XAPIC mode.
Change-Id: I8c458824db1ea66948126622a3e0d0604e391e4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'util/riscv/spike-elf.ld')
0 files changed, 0 insertions, 0 deletions