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author | Julian Schroeder <julianmarcusschroeder@gmail.com> | 2021-09-07 14:54:19 -0500 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-08 20:45:33 +0000 |
commit | 46719834010ce1f4c8ecbc12c9c52baa349ecf9d (patch) | |
tree | e7b1fcf3c593674936dd3660eef8baf7961288e6 /util/riscv/sifive-gpt.py | |
parent | f4a992cca73f227ac86a4e9590198cea72b8b767 (diff) |
soc/amd/cezanne/fsp_m_params: set usb_phy version and length.
Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'util/riscv/sifive-gpt.py')
0 files changed, 0 insertions, 0 deletions