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authorNaresh G Solanki <naresh.solanki@intel.com>2016-11-06 14:12:55 +0530
committerMartin Roth <martinroth@google.com>2016-11-07 20:54:19 +0100
commitb006a3fe5374e0d7b4b0e6e3dc43a55a8f27410a (patch)
tree13bd994c25c41a9588b92d009855458970948f38 /util/nvidia
parent2413cf3dd16dac52e754dcdbc6513b83dd09e0d6 (diff)
mainboard/intel/kblrvp: Configure usb over current pin & cdclock
Configure overcurrent pins for various usb ports. Configure CdClock to 3. Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17251 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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