mb/google/guybrush: Update bootblock power-on timings for PCIe

This configures the bootblock portion of the PCIe GPIOs in the correct
sequence to meet the power-on timings.

Setting the PCIE Reset happens in coreboot instead of in the FSP.

The Aux reset lines are anded with the PCIe RST line, so both have
to be brought up together.  On v1 of guybrush, the PCIe reset line
also resets EC communication, so it must be brought up immediately on
that version.

BUG=b:184796302, b:184598323
TEST=Verify timings between GPIO init sections.  All available modules
are present after training.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

0 files changed, 0 insertions, 0 deletions