diff options
| author | Zhuohao Lee <zhuohao@chromium.org> | 2022-01-18 23:56:16 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-26 19:51:03 +0000 |
| commit | d9e50b1343600398c8922e44de08e394daed3dcf (patch) | |
| tree | 42b1b2484833b9a78c62d52ea90db74da3467295 /util/mainboard/google/brask/template | |
| parent | 2e7b78bad4ffe4dfe8b94255d8fbfbfb76e62109 (diff) | |
util/mb/google: add support for brask
Add the file templates for creating a new variant of Brask.
BUG=b:215091592
TEST=new_variant.py and build coreboot pass for the new variant.
Change-Id: I67e4ed450d6033fed7419bd7c76c127ecd942fe8
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/mainboard/google/brask/template')
3 files changed, 22 insertions, 0 deletions
diff --git a/util/mainboard/google/brask/template/include/variant/ec.h b/util/mainboard/google/brask/template/include/variant/ec.h new file mode 100644 index 0000000000..7a2a6ff8b7 --- /dev/null +++ b/util/mainboard/google/brask/template/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/util/mainboard/google/brask/template/include/variant/gpio.h b/util/mainboard/google/brask/template/include/variant/gpio.h new file mode 100644 index 0000000000..c4fe342621 --- /dev/null +++ b/util/mainboard/google/brask/template/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/util/mainboard/google/brask/template/overridetree.cb b/util/mainboard/google/brask/template/overridetree.cb new file mode 100644 index 0000000000..4f2c04a57a --- /dev/null +++ b/util/mainboard/google/brask/template/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end |