soc/intel/cmn/crashlog: Add check for zero based SRAM BAR

This patch adds a check for zero based SRAM base address. It will
help to avoid running into problems if the SRAM is disabled and
the base address register is zero.

TEST=Able to build and boot google/marasov with PCH SRAM being
disabled.

Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

0 files changed, 0 insertions, 0 deletions