soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code

It implements SPR ramstage including silicon initialization, MSR
programming, MP init and certain registers locking before booting
to payload.

Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

0 files changed, 0 insertions, 0 deletions