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author | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 22:36:28 +0200 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-20 13:18:14 +0000 |
commit | 7db5ce15a3fd8a90cc3bc6c08526358257892cb3 (patch) | |
tree | d488cca798baebaa1487291e1b3412db621d01b5 /util/inteltool/pcie.c | |
parent | 4787f2953cf48eadb8da5b71e85407bbe5abd8b0 (diff) |
sb/intel/i82801dx: Drop unneeded PM2 settings from FADT
The PM2_CNT register block is not present on this southbridge, as per
Intel Document 290744 (ICH4 datasheet). Also, the ACPI specification,
version 6.3, section 4.8.1.3 (PM2 Control Register), says:
This register block is optional, if not supported its block pointer and
length contain a value of zero.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.
Also delete a comment about `pm2_cnt_len`, which said that the right
value differs from zero. Looks like that comment was wrong instead.
Change-Id: Icbb32f5db7b368c764b3477c40f8ae9c788df5ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/inteltool/pcie.c')
0 files changed, 0 insertions, 0 deletions