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| author | Matt DeVillier <matt.devillier@gmail.com> | 2015-05-14 21:58:33 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-05-16 08:14:21 +0200 |
| commit | 5b667df135dc4736f87d0650cc64b2c052bc9b73 (patch) | |
| tree | f2e6fda525a0271aaafd98344d73cec63634250f /util/inteltool/pcie.c | |
| parent | 7780c4f213df157c51ff45f62d644cd90080ae47 (diff) | |
util/inteltool: add Broadwell-U support
add handling of PCI IDs for Broadwell-U/Wildcat Point LP,
using same functions as Haswell-U/Lynx Point LP
Change-Id: I1094cbdace3c73f0f85c2e27c676b877b1a04bfe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10209
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util/inteltool/pcie.c')
| -rw-r--r-- | util/inteltool/pcie.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 6fa94e9ad8..ecfa2f15c9 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -216,6 +216,7 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; @@ -321,6 +322,7 @@ int print_dmibar(struct pci_dev *nb) dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: dmi_registers = haswell_ult_dmi_registers; size = ARRAY_SIZE(haswell_ult_dmi_registers); dmibar_phys = pci_read_long(nb, 0x68); @@ -418,6 +420,7 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; |