diff options
| author | Jason Wang <Qingpei.Wang@amd.com> | 2008-11-28 21:36:51 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-11-28 21:36:51 +0000 |
| commit | f22ce41840ae966a6f465e90c8f05aed9ae5ef6b (patch) | |
| tree | 8cdef566a6d0c3449ab8f12adad0f05e5c6bd4ab /util/flashrom/chipset_enable.c | |
| parent | 4ed326be5d7dec9ee16190847ea0b9f42117fe1a (diff) | |
Add support for the AMD/ATI SB600 southbridge SPI functionality.
This has been tested by Uwe Hermann on an RS690/SB600 board.
Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/flashrom/chipset_enable.c')
| -rw-r--r-- | util/flashrom/chipset_enable.c | 35 |
1 files changed, 25 insertions, 10 deletions
diff --git a/util/flashrom/chipset_enable.c b/util/flashrom/chipset_enable.c index 658313d548..22eceb296e 100644 --- a/util/flashrom/chipset_enable.c +++ b/util/flashrom/chipset_enable.c @@ -647,21 +647,36 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) static int enable_flash_sb600(struct pci_dev *dev, const char *name) { - uint32_t old, new; + uint32_t tmp, low_bits, num; uint8_t reg; - /* Clear ROM Protect 0-3 */ + low_bits = tmp = pci_read_long(dev, 0xa0); + low_bits &= ~0xffffc000; /* for mmap aligning requirements */ + low_bits &= 0xfffffff0; /* remove low 4 bits */ + tmp &= 0xffffc000; + printf_debug("SPI base address is at 0x%x\n", tmp + low_bits); + + sb600_spibar = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, + fd_mem, (off_t)tmp); + if (sb600_spibar == MAP_FAILED) { + perror("Can't mmap memory using " MEM_DEV); + exit(1); + } + sb600_spibar += low_bits; + + /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { - old = pci_read_long(dev, reg); - new = old & 0xFFFFFFFC; - if (new != old) { - pci_write_byte(dev, reg, new); - if (pci_read_long(dev, reg) != new) { - printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x50, new, name); - } - } + num = pci_read_long(dev, reg); + num &= 0xfffffffc; + pci_write_byte(dev, reg, num); } + flashbus = BUS_TYPE_SB600_SPI; + + /* Enable SPI ROM in SB600 PM register. */ + OUTB(0x8f, 0xcd6); + OUTB(0x0e, 0xcd7); + return 0; } |