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authorShaunak Saha <shaunak.saha@intel.com>2020-03-31 22:56:13 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-05-12 20:06:09 +0000
commit32b8a51153f7836b841cb2da832e9e78b32e1227 (patch)
treeec4783ef165c389ed96a56e96545160890474fc9 /util/exynos
parentf318e03495e9a1d43d64516d77a6ae5f2c4d6999 (diff)
soc/intel/tigerlake: Control SATA and DMI power optimization
FSP provides the UPD's for SATA and DMI power optimization. In this patch we are adding the soc's config support to set those power optimization bits in FSP. By default those optimizations are enabled. To disable those we need to set the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1 in devicetree. BUG=b:151162424 BRANCH=None TEST=Build and boot volteer and TGL RVP. Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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