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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-06-28 21:50:43 +0300
committerSven Schnelle <svens@stackframe.org>2012-07-04 14:45:39 +0200
commitae7d6ef8b7ef5ca9c04d8d929332d18d563f723e (patch)
tree4d835a3e4794317b8531585bd3fb54263a00f455 /util/ectool
parent4dcc5737cd431b729a1011c24012d6ee1a481b90 (diff)
Intel model_106cx: change CAR to model_6ex
Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/642 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
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