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authorLijian Zhao <lijian.zhao@intel.com>2017-11-10 17:14:01 -0800
committerAaron Durbin <adurbin@chromium.org>2018-02-16 00:23:04 +0000
commitb716e550338e3da4dcbd9aedbd2c63695ffc8a99 (patch)
tree8d991462f3822e6c27179e2c0101d9027f87c428 /util/crossgcc
parent3faa2c802eaa1ab06c2817af1e234fd839a543c4 (diff)
soc/intel/cannonlake: Add missing GPIO pin definitions
Fill the missing GPIO pin definitions, includeing community 3. Change-Id: I73b7803c73446660f5c25b1263e47bb50a955c56 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22482 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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