summaryrefslogtreecommitdiff
path: root/util/crossgcc/patches
diff options
context:
space:
mode:
authorTim Wawrzynczak <twawrzynczak@chromium.org>2022-08-11 15:58:28 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-08-16 14:20:18 +0000
commit57acfad0bc31dc252d2516de9c04a5cfa93b58b8 (patch)
treeffdd6c9dbc244598fec021ef9fba1e76157d4985 /util/crossgcc/patches
parentb9c7334d8ede7b7095dfde4567374694c51376fa (diff)
mb/google/brya/acpi: Fix GC6 entry and exit sequences
Now that the virtual wire situation is figured out, the GC6 sequence is updated to match the latest HW design guide from Nvidia. This allows Nvidia test software to (mostly) successfully execute the GC6 test, but with some PCIe AER errors. BUG=b:214581763 TEST=tested with Nvidia test software Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia094c4fa9b4db094a59b9b6f02be1a649ee8569b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'util/crossgcc/patches')
0 files changed, 0 insertions, 0 deletions