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authorSubrata Banik <subrata.banik@intel.com>2018-02-20 11:49:45 +0530
committerPatrick Georgi <pgeorgi@google.com>2018-02-22 09:56:37 +0000
commite83d057c3ec3b9a34503008439275777849c0c6a (patch)
treeab7e04792cf134c70382f1356b7486abfde10366 /util/chromeos/extract_blobs.sh
parentf9eaede51848d28214b47ade110b20ceac8a53e2 (diff)
soc/intel/cannonlake: Add provision to make CSME function disable in SMM mode
TEST=lspci from Chrome OS shows CSME device is not visible over PCI tree. Change-Id: I3e0a5b00758a4ce42f2f190748c293c5ce07390c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23824 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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