diff options
| author | Bernardo Perez Priego <bernardo.perez.priego@intel.com> | 2021-05-17 17:37:29 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-01 23:03:35 +0000 |
| commit | ea8a6a2ba20795b70e08714b6b55609db9eaa23e (patch) | |
| tree | f7f638f2743bd0a8078dbba6f53ce7f354a855da /util/cbfstool | |
| parent | de44c0cc36d4e07b38bbf0c0adab76dc145426ea (diff) | |
mb/intel/adlrvp_m: Enable LTR for PCIE
BUG=none
TEST=Use command $ lspci -vv
LTR+ is listed on DevCtl2
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: If65d08a46b9e7304fbe4b92b7f1e6d4e08c599e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54492
Reviewed-by: Ryan A Albazzaz <ryan.a.albazzaz@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/cbfstool')
0 files changed, 0 insertions, 0 deletions