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authorZhao, Lijian <lijian.zhao@intel.com>2016-01-20 13:02:38 -0800
committerMartin Roth <martinroth@google.com>2016-04-11 18:23:08 +0200
commit51d43fc9c5aab428d589b602759476d716fbea6e (patch)
treef34c04ce843bc18cb0c85923489d5d51b5ae8eef /util/cbfstool/compress.c
parent30461a91977d6770bb3ec6c378a21afe2616f3d7 (diff)
soc/intel/apollolake: Add lpss dsdt entry
Add southbridge and LPSS device DSDT table. Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14218 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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