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author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-22 10:37:49 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 14:23:32 +0000 |
commit | 8297fa1e206c7d0a5628661f4ed57f768a676ebe (patch) | |
tree | db2f82d682683bd26b5fd2b366e7f1cb8bcc0f1a /util/README.md | |
parent | 6a4f46ac5e2abe2a33600135bbad36cf14b23881 (diff) |
util: Remove old reference to ROMCC
Change-Id: Ia1a37db8341281102ae8ae9c03f1ce76d8d126eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39075
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/README.md')
-rw-r--r-- | util/README.md | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/util/README.md b/util/README.md index 55bcaab637..66438a9ce9 100644 --- a/util/README.md +++ b/util/README.md @@ -86,8 +86,6 @@ can be passed to SPIKE, the RISC-V reference emulator.`Bash` * _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for SiFive's bootrom. `Python3` * __rockchip__ - Generate Rockchip idblock bootloader. `Python2` -* __romcc__ - Compile a C source file generating a binary that does not -implicitly use RAM. `C` * __sconfig__ - coreboot device tree compiler `Lex` `Yacc` * __scripts__ * _config_ - Manipulate options in a .config file from the |