soc/intel/tigerlake: Add Acoustic features

Expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRateFor

BUG=b:153015585
BRANCH=none
TEST= Measure the change in noise level by changing the UPD values.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I1924a3bac8beb16a9d841891696f9a3dea0d425f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

0 files changed, 0 insertions, 0 deletions