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authorFelix Held <felix-coreboot@felixheld.de>2023-06-01 22:06:53 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-06-07 00:29:39 +0000
commitf6421311c96fd3ffef0e9b4791c9c25a2f03d055 (patch)
treea6a0c62ffece241565facbd8278fe5d6687fb28c /tests/data/lib
parent4d6c39d4f41b4d7dbfbb1df04390ccafbc487b42 (diff)
soc/amd/stoneyridge/acpi: use ROOT_BRIDGE macro
Instead of having the different static parts of the PCI0 device in northbridge.asl and sb_pci0_fch.asl, instantiate the static parts of the PCI0 device via the ROOT_BRIDGE macro in soc.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4a9af2fd853f4e993e71158c5e85052084b50cdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75596 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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