newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 0 insertions, 427 deletions

diff --git a/targets/iwill/dk8_htx/Config-abuild.lb b/targets/iwill/dk8_htx/Config-abuild.lb
deleted file mode 100644
index 22e527e6d4..0000000000
--- a/targets/iwill/dk8_htx/Config-abuild.lb
+++ /dev/null
@@ -1,34 +0,0 @@
-# This will make a target directory of ./VENDOR_MAINBOARD
-
-target VENDOR_MAINBOARD
-mainboard VENDOR/MAINBOARD
-
-option CC="CROSSCC"
-option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
-
-__COMPRESSION__
-__LOGLEVEL__
-
-romimage "normal"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option COREBOOT_EXTRA_VERSION=".0-normal"
-	payload __PAYLOAD__
-end
-
-romimage "fallback"
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option COREBOOT_EXTRA_VERSION=".0-fallback"
-	payload __PAYLOAD__
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/iwill/dk8_htx/Config.lb b/targets/iwill/dk8_htx/Config.lb
deleted file mode 100644
index 460dcc417d..0000000000
--- a/targets/iwill/dk8_htx/Config.lb
+++ /dev/null
@@ -1,74 +0,0 @@
-
-target dk8_htx
-mainboard iwill/dk8_htx
-
-# serengeti_leopard
-romimage "normal"
-#       48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 475136
-#       48K for SCSI FW and 48K for ATI ROM
-#       option CONFIG_ROM_SIZE = 425984 
-#       64K for Etherboot
-#        option CONFIG_ROM_SIZE = 458752 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=0
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#       payload ../../../../payloads/e1000--filo.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "fallback" 
-	option CONFIG_USE_FAILOVER_IMAGE=0
-	option CONFIG_USE_FALLBACK_IMAGE=1
-#	option CONFIG_ROM_IMAGE_SIZE=0x13800
-#	option CONFIG_ROM_IMAGE_SIZE=0x17800
-#	option CONFIG_ROM_IMAGE_SIZE=0x15800
-	option CONFIG_ROM_IMAGE_SIZE=0x20000
-	option CONFIG_XIP_ROM_SIZE=0x20000
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-#       payload ../../../payloads/tg3--ide_disk.zelf
-#        payload ../../../payloads/filo.elf
-#        payload ../../../payloads/filo_mem.elf
-#        payload ../../../payloads/filo.zelf
-#        payload ../../../payloads/tg3--filo_hda2.zelf
-#	payload ../../../payloads/tg3.zelf
-#	payload ../../../payloads/tg3_vga.zelf
-#	payload ../../../../payloads/memtest
-#	payload ../../../../payloads/tg3--filo_hda2_vga.zelf
-	payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-#	payload ../../../payloads/tg3_com2.zelf
-#       payload ../../../../payloads/e1000--filo.zelf
-#        payload ../../../payloads/tg3--e1000--filo.zelf
-#        payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-#	payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
-	option CONFIG_USE_FAILOVER_IMAGE=1
-        option CONFIG_USE_FALLBACK_IMAGE=0
-        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
-        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/iwill/dk8_htx/VERSION b/targets/iwill/dk8_htx/VERSION
deleted file mode 100644
index 5755a12232..0000000000
--- a/targets/iwill/dk8_htx/VERSION
+++ /dev/null
@@ -1 +0,0 @@
-_dk8_htx
diff --git a/targets/iwill/dk8s2/Config.lb b/targets/iwill/dk8s2/Config.lb
deleted file mode 100644
index ff9aeb468e..0000000000
--- a/targets/iwill/dk8s2/Config.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-# Sample config file for 
-# the Iwill DK8S2
-# This will make a target directory of ./dk8s2
-
-target dk8s2
-
-mainboard iwill/dk8s2
-
-option CONFIG_HAVE_HARD_RESET=1
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_HAVE_MP_TABLE=1
-option CONFIG_ROM_SIZE=1024*1024
-
-option CONFIG_HAVE_FALLBACK_BOOT=1
-  
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_IRQ_SLOT_COUNT=12
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-#option CONFIG_LOGICAL_CPUS=1
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable 
-### caching from 640KB-1MB using fixed MTRRs 
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option CONFIG_MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option CONFIG_MAINBOARD_PART_NUMBER="DK8S2"
-option CONFIG_MAINBOARD_VENDOR="IWILL"
-#
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-#option CONFIG_FALLBACK_SIZE=524288
-#option CONFIG_FALLBACK_SIZE=98304
-option CONFIG_FALLBACK_SIZE=131072
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-option CONFIG_ROM_IMAGE_SIZE=65536
- 
-
-###
-### Compute where this copy of coreboot will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-#option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option CONFIG_TTYS0_BAUD=115200
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7
-
-#option CONFIG_DEBUG=1
-
-#
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option CONFIG_STACK_SIZE=0x8000 
-
-##
-## Use a 56K heap
-##
-option CONFIG_HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-option CONFIG_ROM_PAYLOAD     = 1
-
-#
-# 
-romimage "normal"
-#	48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#	48K for SCSI FW and 48K for ATI ROM
-#	option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_SECTION_SIZE  = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
-	option CONFIG_ROM_SECTION_OFFSET= 0
-
-#	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
-        option CONFIG_XIP_ROM_SIZE = 65536
-
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
-
-	payload /usr/src/filo-0.4.1_btext/filo.elf
-#	payload /usr/src/filo-0.4.2/filo.elf
-end
-
-romimage "fallback" 
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_SECTION_SIZE  = CONFIG_FALLBACK_SIZE
-	option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
-
-#	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
-	option CONFIG_XIP_ROM_SIZE = 65536
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
-
-	payload ../../../payloads/filo.elf
-#	payload /usr/src/filo-0.4.2/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/iwill/dk8x/Config.lb b/targets/iwill/dk8x/Config.lb
deleted file mode 100644
index 54bd4a1f01..0000000000
--- a/targets/iwill/dk8x/Config.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-# Sample config file for 
-# the Iwill DK8X
-# This will make a target directory of ./dk8x
-
-target dk8x
-
-mainboard iwill/dk8x
-
-option CONFIG_HAVE_HARD_RESET=1
-
-option CONFIG_HAVE_OPTION_TABLE=1
-option CONFIG_HAVE_MP_TABLE=1
-option CONFIG_ROM_SIZE=1024*1024
-
-option CONFIG_HAVE_FALLBACK_BOOT=1
-  
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option CONFIG_GENERATE_PIRQ_TABLE=1
-option CONFIG_IRQ_SLOT_COUNT=12
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-#option CONFIG_LOGICAL_CPUS=1
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### CONFIG_MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable 
-### caching from 640KB-1MB using fixed MTRRs 
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option CONFIG_MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option CONFIG_MAINBOARD_PART_NUMBER="DK8X"
-option CONFIG_MAINBOARD_VENDOR="IWILL"
-#
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-#option CONFIG_FALLBACK_SIZE=524288
-#option CONFIG_FALLBACK_SIZE=98304
-option CONFIG_FALLBACK_SIZE=131072
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-option CONFIG_ROM_IMAGE_SIZE=65536
- 
-
-###
-### Compute where this copy of coreboot will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-#option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option CONFIG_TTYS0_BAUD=115200
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=7
-
-#option CONFIG_DEBUG=1
-
-#
-
-## Coreboot C code runs at this location in RAM
-option CONFIG_RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option CONFIG_STACK_SIZE=0x8000 
-
-##
-## Use a 56K heap
-##
-option CONFIG_HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The coreboot bootloader.
-###
-option CONFIG_ROM_PAYLOAD     = 1
-
-#
-# 
-romimage "normal"
-#	48K for SCSI FW
-#        option CONFIG_ROM_SIZE = 512*1024-48*1024
-#	48K for SCSI FW and 48K for ATI ROM
-#	option CONFIG_ROM_SIZE = 512*1024-48*1024-48*1024
-        option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-	option CONFIG_USE_FALLBACK_IMAGE=0
-	option CONFIG_ROM_SECTION_SIZE  = (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
-	option CONFIG_ROM_SECTION_OFFSET= 0
-
-#	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
-        option CONFIG_XIP_ROM_SIZE = 65536
-
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
-
-	payload /usr/src/filo-0.4.1_btext/filo.elf
-#	payload /usr/src/filo-0.4.2/filo.elf
-end
-
-romimage "fallback" 
-	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-	option CONFIG_USE_FALLBACK_IMAGE=1
-	option CONFIG_ROM_SECTION_SIZE  = CONFIG_FALLBACK_SIZE
-	option CONFIG_ROM_SECTION_OFFSET= (CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE)
-
-#	option CONFIG_XIP_ROM_SIZE = CONFIG_FALLBACK_SIZE
-	option CONFIG_XIP_ROM_SIZE = 65536
-	option CONFIG_XIP_ROM_BASE = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE)
-
-	payload ../../../payloads/filo.elf
-#	payload /usr/src/filo-0.4.2/filo.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"