AGESA: Avoid cpuRegisters.h include

Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

9 files changed, 7 insertions, 16 deletions

diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 4dbe86d3d9..735e126bb9 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -35,7 +35,6 @@
 #include <AGESA.h>
 #include <Options.h>
 #include <Topology.h>
-#include <cpuRegisters.h>
 
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
@@ -931,7 +930,7 @@ static void cpu_bus_scan(device_t dev)
 #endif
 
 	/* Get Max Number of cores(MNC) */
-	coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+	coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
 	core_max = 1 << (coreid_bits & 0x000F); //mnc
 
 	ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index e82dae17d9..675be14182 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -36,7 +36,6 @@
 #include <Porting.h>
 #include <Options.h>
 #include <Topology.h>
-#include <cpuRegisters.h>
 
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
@@ -921,7 +920,7 @@ static void cpu_bus_scan(device_t dev)
 #endif
 
 	/* Get Max Number of cores(MNC) */
-	coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+	coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
 	core_max = 1 << (coreid_bits & 0x000F); //mnc
 
 	ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 77215b4ae6..557c9c4bbd 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -35,7 +35,6 @@
 #include <AGESA.h>
 #include <Options.h>
 #include <Topology.h>
-#include <cpuRegisters.h>
 
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
@@ -937,7 +936,7 @@ static void cpu_bus_scan(device_t dev)
 #endif
 
 	/* Get Max Number of cores(MNC) */
-	coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+	coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
 	core_max = 1 << (coreid_bits & 0x000F); //mnc
 
 	ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index cb90cb61f0..f24a4818a0 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -32,7 +32,6 @@
 #include <FieldAccessors.h>
 #include <Options.h>
 #include <Topology.h>
-#include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
@@ -935,7 +934,7 @@ static void cpu_bus_scan(device_t dev)
 #endif
 
 	/* Get Max Number of cores(MNC) */
-	coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+	coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
 	core_max = 1 << (coreid_bits & 0x000F); //mnc
 
 	ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 1f2c28ed77..6a2cb8fac2 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -32,7 +32,6 @@
 #include <FieldAccessors.h>
 #include <Options.h>
 #include <Topology.h>
-#include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
@@ -934,7 +933,7 @@ static void cpu_bus_scan(device_t dev)
 #endif
 
 	/* Get Max Number of cores(MNC) */
-	coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+	coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
 	core_max = 1 << (coreid_bits & 0x000F); //mnc
 
 	ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 9014f29ee3..a762e2c46d 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -32,7 +32,6 @@
 #include <FieldAccessors.h>
 #include <Options.h>
 #include <Topology.h>
-#include <cpuRegisters.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
@@ -960,7 +959,7 @@ static void cpu_bus_scan(device_t dev)
 #endif
 
 	/* Get Max Number of cores(MNC) */
-	coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+	coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12;
 	core_max = 1 << (coreid_bits & 0x000F); //mnc
 
 	ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 2fb708bafa..d9123172f7 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -18,7 +18,6 @@
 #include <cbmem.h>
 #include <delay.h>
 #include <cpu/x86/mtrr.h>
-#include <cpuRegisters.h>
 #include <FchPlatform.h>
 #include <heapManager.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c
index 3ad487169e..b95d61ab6a 100644
--- a/src/soc/amd/common/agesawrapper.c
+++ b/src/soc/amd/common/agesawrapper.c
@@ -18,7 +18,6 @@
 #include <cbmem.h>
 #include <delay.h>
 #include <cpu/x86/mtrr.h>
-#include <cpuRegisters.h>
 #include <FchPlatform.h>
 #include <heapManager.h>
 #include <agesawrapper.h>
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index c0f5850155..d9cc281ef3 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -40,7 +40,6 @@
  * and not set by vendorcode
  */
 #include <AGESA.h>
-#include <cpuRegisters.h>
 #include <FieldAccessors.h>
 #include <Options.h>
 #include <Porting.h>
@@ -573,7 +572,7 @@ void cpu_bus_scan(device_t dev)
 	}
 
 	/* Get max and actual number of cores */
-	pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT);
+	pccount = cpuid_ecx(0x80000008);
 	core_max = 1 << ((pccount >> 12) & 0xf);
 	core_nums = (pccount & 0xF);