diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2024-04-17 10:45:15 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-10-31 13:47:32 +0000 |
| commit | affb04de0b45ba4ea0dcaf339ea2128388f67f40 (patch) | |
| tree | 15a983fc80c76c834f9996e87fb627780d149212 /src | |
| parent | d99640ffe586fe018d35e3636d63538c26d07f6c (diff) | |
mb/google/rauru: Pre-initialize PCIe at the bootblock stage
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. Right now we simply
wait for 100ms in ramstage for that.
To speed up the boot time, pre-initialize PCIe by asserting PERST#
earlier in the bootblock stage. The pre-initialization time is stored
in the early init data region, so that the PCIe initialization in
ramstage could make sure the required 100ms delay is still reached.
This pre-initialization will speed up the boot time by 100ms on rauru.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rauru/bootblock.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index b1f986369e..e0717aa57a 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <gpio.h> +#include <soc/pcie.h> #include <soc/spi.h> #include "gpio.h" @@ -13,6 +14,9 @@ static void usb3_hub_reset(void) void bootblock_mainboard_init(void) { + if (CONFIG(PCI)) + mtk_pcie_pre_init(); + mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios(); |