diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 15:49:55 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-19 11:19:51 +0000 |
| commit | afc6c0ae12ddd26c05bcc2fa527c7a15d0bca0ad (patch) | |
| tree | db3d89c2712162e04577e2230984778c5ec9f869 /src | |
| parent | 260e98fbe7c0aed5cbb1e4360fbaed32711e88d3 (diff) | |
mb/google/slippy: Correct memory-down SPD handling
MRC only uses the SPD data for the first index, and ignores the rest.
Moreover, index 1 corresponds to the second DIMM on the first channel,
which does not exist on ULT (only one DIMM per channel is supported).
Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge
code to retrieve the serial number from the correct SPD data block.
Tested on Google Wolf, both channels are still correctly detected.
Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
5 files changed, 10 insertions, 9 deletions
diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 21a4ec62be..05b4eb78c5 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -18,7 +18,7 @@ void copy_spd(struct pei_data *peid) */ switch (spd_index) { case 0: case 1: case 2: case 6: - memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); + memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN); break; case 3: case 4: case 5: case 7: peid->dimm_channel1_disabled = 3; diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 938590b4f0..2e5dee195e 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -19,7 +19,7 @@ void copy_spd(struct pei_data *peid) if (spd_index & 0x4) peid->dimm_channel1_disabled = 3; else - memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); + memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN); } const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 02b47db97f..12e2714b6d 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -24,7 +24,7 @@ void copy_spd(struct pei_data *peid) if (spd_index == 0) peid->dimm_channel1_disabled = 3; else - memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); + memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN); break; case PEPPY_BOARD_VERSION_EVT: @@ -34,7 +34,7 @@ void copy_spd(struct pei_data *peid) if (spd_index > 3) peid->dimm_channel1_disabled = 3; else - memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); + memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN); break; } } diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 939d58403f..05e128d87e 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -18,7 +18,7 @@ void copy_spd(struct pei_data *peid) */ switch (spd_index) { case 0: case 1: case 2: - memcpy(peid->spd_data[1], peid->spd_data[0], SPD_LEN); + memcpy(peid->spd_data[2], peid->spd_data[0], SPD_LEN); break; case 3: case 4: case 5: peid->dimm_channel1_disabled = 3; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 58ac8a05a3..c85ca5bb7b 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -227,6 +227,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) for (d_num = 0; d_num < NUM_SLOTS; d_num++) { const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256; if (dimm_size) { + const int index = ch * NUM_SLOTS + d_num; dimm = &mem_info->dimm[dimm_cnt]; dimm->dimm_size = dimm_size; dimm->ddr_type = MEMORY_TYPE_DDR3; @@ -236,14 +237,14 @@ void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = d_num; dimm->bank_locator = ch * 2; memcpy(dimm->serial, - &pei_data->spd_data[dimm_cnt][SPD_DIMM_SERIAL_NUM], + &pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM], SPD_DIMM_SERIAL_LEN); memcpy(dimm->module_part_number, - &pei_data->spd_data[dimm_cnt][SPD_DIMM_PART_NUM], + &pei_data->spd_data[index][SPD_DIMM_PART_NUM], SPD_DIMM_PART_LEN); dimm->mod_id = - (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xff); + (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) | + (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff); dimm->mod_type = SPD_SODIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; |