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authorMaximilian Brune <maximilian.brune@9elements.com>2024-08-09 12:49:29 +0200
committerMartin L Roth <gaumless@gmail.com>2024-09-30 15:50:16 +0000
commitaed7a871b2520eff698dde22ffdae37f971bd92c (patch)
tree1065fde82a9b3b37e91518aed113bf2e79619140 /src
parent16110c077840a5baab7fcc1f0f61324c59fc68e3 (diff)
soc/amd/glinda: Update gpp bridge naming scheme
This patch updates the naming scheme used for the GPP bridges. The naming scheme now matches what we also have on phoenix. Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/birman/devicetree_glinda.cb7
-rw-r--r--src/mainboard/amd/birman_plus/devicetree_glinda.cb6
-rw-r--r--src/soc/amd/glinda/chipset.cb14
3 files changed, 15 insertions, 12 deletions
diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb
index f1a99f6994..2e06f2b4b4 100644
--- a/src/mainboard/amd/birman/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman/devicetree_glinda.cb
@@ -158,9 +158,10 @@ chip soc/amd/glinda
device domain 0 on
device ref iommu on end
- device ref gpp_bridge_0 on end # GBE
- device ref gpp_bridge_1 on end # WIFI
- device ref gpp_bridge_2 on end # NVMe SSD
+ device ref gpp_bridge_2_1 on end # GBE
+ device ref gpp_bridge_2_2 on end # WIFI
+ device ref gpp_bridge_2_3 on end # NVMe SSD
+
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
index 1df02ed004..e867f018fc 100644
--- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb
+++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb
@@ -158,9 +158,9 @@ chip soc/amd/glinda
device domain 0 on
device ref iommu on end
- device ref gpp_bridge_0 on end # GBE
- device ref gpp_bridge_1 on end # WIFI
- device ref gpp_bridge_2 on end # NVMe SSD
+ device ref gpp_bridge_2_1 on end # GBE
+ device ref gpp_bridge_2_2 on end # WIFI
+ device ref gpp_bridge_2_3 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb
index 6e23c2d4c2..f328797ec2 100644
--- a/src/soc/amd/glinda/chipset.cb
+++ b/src/soc/amd/glinda/chipset.cb
@@ -14,13 +14,15 @@ chip soc/amd/glinda
device pci 01.2 alias usb4_pcie_bridge_1 off end
device pci 01.3 alias usb4_pcie_bridge_2 off end
+ # The PCIe GPP aliases in this SoC match the device and function numbers
device pci 02.0 on end # Dummy device function, do not disable
- device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end
- device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end
- device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end
- device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end
- device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end
- device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
+ device pci 02.1 alias gpp_bridge_2_1 off ops amd_external_pcie_gpp_ops end
+ device pci 02.2 alias gpp_bridge_2_2 off ops amd_external_pcie_gpp_ops end
+ device pci 02.3 alias gpp_bridge_2_3 off ops amd_external_pcie_gpp_ops end
+ device pci 02.4 alias gpp_bridge_2_4 off ops amd_external_pcie_gpp_ops end
+ device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end
+ device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end
+
device pci 03.0 on end # Dummy device function, do not disable
device pci 03.1 alias gpp_bridge_3_1 off ops amd_external_pcie_gpp_ops end
device pci 03.2 alias gpp_bridge_3_2 off ops amd_external_pcie_gpp_ops end