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authorDuncan Laurie <dlaurie@google.com>2020-11-09 09:36:31 -0800
committerDuncan Laurie <dlaurie@chromium.org>2020-11-20 00:25:19 +0000
commit9d0fde3dc57bddf3a8e27bedcb35bbccfec1099a (patch)
tree9fc2a7e4da22f834e2effbaf7e7817c1f1a1cf68 /src
parente1490e55edfed6acfc3e06e5117cabccd2704a11 (diff)
mb/google/volteer: Enable RTD3 for SD card
Enable the PCIe RTD3 driver for the PCIe attached SD card interface and provide the enable/reset GPIOs. These GPIOs are common across all variants so this is implemented in the baseboard devicetree with an fw_config probe if the device is present. The RTS5261 device does not have an enable GPIO so it is disabled in a workaround in mainboard.c, along with marking the SD-Express device as external. BUG=b:162289926, b:162289982 TEST=Tested on Delbin platform to ensure the system can enter the S0i3.2 substate and suspend/resume is stable. enabling this for the regular Genesys Change-Id: I40fe05829783c7bce2a2c4c1520a4a7430642e26 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/volteer/fw_config.c8
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb21
2 files changed, 28 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c
index 4067fa526a..50e8f93080 100644
--- a/src/mainboard/google/volteer/fw_config.c
+++ b/src/mainboard/google/volteer/fw_config.c
@@ -66,6 +66,10 @@ static const struct pad_config i2s_disable_pads[] = {
PAD_NC(GPP_R7, NONE),
};
+static const struct pad_config sd_gl9755s_pads[] = {
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+};
+
static void fw_config_handle(void *unused)
{
if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) {
@@ -94,5 +98,9 @@ static void fw_config_handle(void *unused)
gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
}
+ if (fw_config_probe(FW_CONFIG(DB_SD, SD_GL9755S))) {
+ printk(BIOS_INFO, "Configure GPIOs for SD GL9755S.\n");
+ gpio_configure_pads(sd_gl9755s_pads, ARRAY_SIZE(sd_gl9755s_pads));
+ }
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 50be7367da..fa807ba40f 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -445,7 +445,26 @@ chip soc/intel/tigerlake
device ref sata on end
device ref pcie_rp1 on end
device ref pcie_rp7 on end
- device ref pcie_rp8 on end
+ device ref pcie_rp8 on
+ probe DB_SD SD_GL9755S
+ probe DB_SD SD_RTS5261
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)"
+ register "srcclk_pin" = "3"
+ device generic 0 on
+ probe DB_SD SD_GL9755S
+ end
+ end
+ chip soc/intel/common/block/pcie/rtd3
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)"
+ register "srcclk_pin" = "3"
+ register "is_external" = "1"
+ device generic 1 on
+ probe DB_SD SD_RTS5261
+ end
+ end
+ end
device ref pcie_rp9 on end
device ref pcie_rp11 on end
device ref uart0 on end