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authorAngel Pons <th3fanbus@gmail.com>2021-02-10 12:43:02 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-12 07:56:33 +0000
commit9382f0c251f64ac3f469a19ab08da9d7a548a99c (patch)
treec6e5551036bf09beee5b31547ff1b658e4b59e93 /src
parent04f1de3e149140f58358659c5977515ea36f17f7 (diff)
sb/intel/lynxpoint: Do not mask out TCO status bits
Not all TCO status bits have a corresponding enable bit. Masking out the status register with the enable register causes these events to be lost. Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected. Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/lynxpoint/pmutil.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 7b8468934f..8117b4d3ea 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -298,12 +298,11 @@ void enable_alt_smi(u32 mask)
* TCO
*/
-/* Clear TCO status and return events that are enabled and active */
+/* Clear TCO status and return events that are active */
static u32 reset_tco_status(void)
{
u32 tcobase = get_pmbase() + 0x60;
u32 tco_sts = inl(tcobase + 0x04);
- u32 tco_en = inl(get_pmbase() + 0x68);
/* Don't clear BOOT_STS before SECOND_TO_STS */
outl(tco_sts & ~(1 << 18), tcobase + 0x04);
@@ -312,7 +311,7 @@ static u32 reset_tco_status(void)
if (tco_sts & (1 << 18))
outl(tco_sts & (1 << 18), tcobase + 0x04);
- return tco_sts & tco_en;
+ return tco_sts;
}
/* Print TCO status bits */