diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2023-04-26 19:42:50 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-04-27 14:40:27 +0000 |
| commit | 78790c872c8bae4d0fc2cc4614fa9619c69116cd (patch) | |
| tree | 218231e6279fa480c76c8057fe2c4a118e246d9b /src | |
| parent | c2059fa72a654f8927f05bcecb4d98ef856c9b64 (diff) | |
vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vaule
Add UPD edp_panel_t9_ms for eDP panel sequence adjustment.
BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/vendorcode/amd/fsp/mendocino/FspmUpd.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h index b3d6dc39d9..e2622dde44 100644 --- a/src/vendorcode/amd/fsp/mendocino/FspmUpd.h +++ b/src/vendorcode/amd/fsp/mendocino/FspmUpd.h @@ -102,7 +102,8 @@ typedef struct __packed { /** Offset 0x04E5**/ uint32_t vrm_soc_current_limit_mA; /** Offset 0x04E9**/ uint8_t fch_usb_3_port_force_gen1; /** Offset 0x04EA**/ uint8_t edp_panel_t8_ms; - /** Offset 0x04EB**/ uint8_t UnusedUpdSpace2[277]; + /** Offset 0x04EB**/ uint8_t edp_panel_t9_ms; + /** Offset 0x04EC**/ uint8_t UnusedUpdSpace2[276]; /** Offset 0x0600**/ uint16_t UpdTerminator; } FSP_M_CONFIG; |