diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2024-07-23 11:54:30 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-06 13:14:40 +0000 |
| commit | 4e1ed767ab26deccc7b1b65b5b556d693dd6053e (patch) | |
| tree | 6d39fdbdee34754cac05373cb5dc2a5b7e9bd1f7 /src | |
| parent | 9f6cb3e6117665b3aef3d90d963a7d2e260050ff (diff) | |
mb/google/brox/variants/brox: Update PL1 Min
Update PL1 Min value from 6W to 15W based on the brox thermal cooling
capacity and hardware design.
BUG=None
BRANCH=None
TEST=Build and boot on brox board
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brox/variants/brox/ramstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brox/variants/brox/ramstage.c b/src/mainboard/google/brox/variants/brox/ramstage.c index c81dd7e8be..78e03caccb 100644 --- a/src/mainboard/google/brox/variants/brox/ramstage.c +++ b/src/mainboard/google/brox/variants/brox/ramstage.c @@ -16,7 +16,7 @@ const struct cpu_power_limits performance_efficient_limits[] = { { .mchid = PCI_DID_INTEL_RPL_P_ID_3, .cpu_tdp = 15, - .pl1_min_power = 6000, + .pl1_min_power = 15000, .pl1_max_power = 15000, .pl2_min_power = 55000, .pl2_max_power = 55000, @@ -25,7 +25,7 @@ const struct cpu_power_limits performance_efficient_limits[] = { { .mchid = PCI_DID_INTEL_RPL_P_ID_4, .cpu_tdp = 15, - .pl1_min_power = 6000, + .pl1_min_power = 15000, .pl1_max_power = 15000, .pl2_min_power = 55000, .pl2_max_power = 55000, |