soc/amd/stoneyridge: Use new common SPI code

Use the new SPI code from common folder, delete spi.c. SPI related macros
must be single defined, in southbridge.h if they are used by files other
than the common SPI code, fch_spi.h if they are only used by the common
SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h,
because it can change between SOC.

BUG=b:136595978
TEST=Build and boot grunt using new SPI code, with debug enabled. Check
output.

Change-Id: I639973d993316a10daa7564462e689b2c183f536
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>

5 files changed, 12 insertions, 209 deletions

diff --git a/src/soc/amd/common/block/include/amdblocks/fch_spi.h b/src/soc/amd/common/block/include/amdblocks/fch_spi.h
index 24cfbfc74a..cfbdf198b5 100644
--- a/src/soc/amd/common/block/include/amdblocks/fch_spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/fch_spi.h
@@ -28,13 +28,21 @@
 #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
 
 /* SPI MMIO registers */
-#define SPI_CNTRL0			0x00
-#define   SPI_ACCESS_MAC_ROM_EN		BIT(22)
 #define SPI_RESTRICTED_CMD1		0x04
 #define SPI_RESTRICTED_CMD2		0x08
 #define SPI_CNTRL1			0x0c
 #define SPI_CMD_CODE			0x45
 #define SPI_CMD_TRIGGER			0x47
+#define   SPI_CMD_TRIGGER_EXECUTE	BIT(7)
+#define SPI_TX_BYTE_COUNT		0x48
+#define SPI_RX_BYTE_COUNT		0x4b
+#define SPI_STATUS			0x4c
+#define   SPI_DONE_BYTE_COUNT_SHIFT	0
+#define   SPI_DONE_BYTE_COUNT_MASK	0xff
+#define   SPI_FIFO_WR_PTR_SHIFT		8
+#define   SPI_FIFO_WR_PTR_MASK		0x7f
+#define   SPI_FIFO_RD_PTR_SHIFT		16
+#define   SPI_FIFO_RD_PTR_MASK		0x7f
 
 /* Special SST write commands */
 #define CMD_SST_BP			0x02	/* Byte Program */
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index f1d08c03d7..72719d7179 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -52,7 +52,7 @@ config CPU_SPECIFIC_OPTIONS
 	select GENERIC_UDELAY
 	select IOAPIC
 	select HAVE_USBDEBUG_OPTIONS
-	select SPI_FLASH if HAVE_ACPI_RESUME
+	select SOC_AMD_COMMON_BLOCK_SPI
 	select TSC_SYNC_LFENCE
 	select COLLECT_TIMESTAMPS
 	select SOC_AMD_PI
diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 0fed074523..53aabf5d65 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -49,7 +49,6 @@ bootblock-y += reset.c
 bootblock-y += tsc_freq.c
 bootblock-y += southbridge.c
 bootblock-y += nb_util.c
-bootblock-$(CONFIG_SPI_FLASH) += spi.c
 bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 
 romstage-y += BiosCallOuts.c
@@ -67,7 +66,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 romstage-y += tsc_freq.c
 romstage-y += southbridge.c
 romstage-y += nb_util.c
-romstage-$(CONFIG_SPI_FLASH) += spi.c
 romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 
 verstage-y += gpio.c
@@ -78,7 +76,6 @@ verstage-y += reset.c
 verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 verstage-y += tsc_freq.c
 verstage-y += nb_util.c
-verstage-$(CONFIG_SPI_FLASH) += spi.c
 
 postcar-y += monotonic_timer.c
 postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
@@ -109,7 +106,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 ramstage-y += usb.c
 ramstage-y += tsc_freq.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
 ramstage-y += finalize.c
 ramstage-y += nb_util.c
 
@@ -118,7 +114,6 @@ smm-y += smihandler.c
 smm-y += smi_util.c
 smm-y += tsc_freq.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
-smm-$(CONFIG_SPI_FLASH) += spi.c
 smm-y += nb_util.c
 smm-y += gpio.c
 
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 07c92a185c..dd514ab88f 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -265,22 +265,10 @@
 #define   SPI_READ_MODE_QUAD144		(BIT(30) |           BIT(18))
 #define   SPI_READ_MODE_NORMAL66	(BIT(30) | BIT(29)          )
 #define   SPI_READ_MODE_FAST		(BIT(30) | BIT(29) | BIT(18))
+#define   SPI_ACCESS_MAC_ROM_EN		BIT(22)
 #define   SPI_FIFO_PTR_CLR		BIT(20)
 #define   SPI_ARB_ENABLE		BIT(19)
 #define   EXEC_OPCODE			BIT(16)
-#define SPI_CNTRL1			0x0c
-#define SPI_CMD_CODE			0x45
-#define SPI_CMD_TRIGGER			0x47
-#define   SPI_CMD_TRIGGER_EXECUTE	BIT(7)
-#define SPI_TX_BYTE_COUNT		0x48
-#define SPI_RX_BYTE_COUNT		0x4b
-#define SPI_STATUS			0x4c
-#define   SPI_DONE_BYTE_COUNT_SHIFT	0
-#define   SPI_DONE_BYTE_COUNT_MASK	0xff
-#define   SPI_FIFO_WR_PTR_SHIFT		8
-#define   SPI_FIFO_WR_PTR_MASK		0x7f
-#define   SPI_FIFO_RD_PTR_SHIFT		16
-#define   SPI_FIFO_RD_PTR_MASK		0x7f
 #define SPI_FIFO			0x80
 #define   SPI_FIFO_DEPTH		(0xc7 - SPI_FIFO)
 
diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c
deleted file mode 100644
index 60b6a20dbe..0000000000
--- a/src/soc/amd/stoneyridge/spi.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/mmio.h>
-#include <lib.h>
-#include <timer.h>
-#include <console/console.h>
-#include <commonlib/helpers.h>
-#include <spi_flash.h>
-#include <spi-generic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/southbridge.h>
-#include <amdblocks/lpc.h>
-#include <soc/pci_devs.h>
-
-#define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH)
-
-static uintptr_t spibar;
-
-static void set_spibar(uintptr_t base)
-{
-	spibar = base;
-}
-
-static inline uint8_t spi_read8(uint8_t reg)
-{
-	return read8((void *)(spibar + reg));
-}
-
-static inline uint32_t spi_read32(uint8_t reg)
-{
-	return read32((void *)(spibar + reg));
-}
-
-static inline void spi_write8(uint8_t reg, uint8_t val)
-{
-	write8((void *)(spibar + reg), val);
-}
-
-static inline void spi_write32(uint8_t reg, uint32_t val)
-{
-	write32((void *)(spibar + reg), val);
-}
-
-static void dump_state(const char *str)
-{
-	if (!SPI_DEBUG_DRIVER)
-		return;
-
-	printk(BIOS_DEBUG, "SPI: %s\n", str);
-	printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0));
-	printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS));
-	printk(BIOS_DEBUG, "TxByteCount: %x\n", spi_read8(SPI_TX_BYTE_COUNT));
-	printk(BIOS_DEBUG, "RxByteCount: %x\n", spi_read8(SPI_RX_BYTE_COUNT));
-	printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE));
-	hexdump((void *)(spibar + SPI_FIFO), SPI_FIFO_DEPTH);
-}
-
-static int wait_for_ready(void)
-{
-	const uint32_t timeout_ms = 500;
-	struct stopwatch sw;
-
-	stopwatch_init_msecs_expire(&sw, timeout_ms);
-
-	do {
-		if (!(spi_read32(SPI_STATUS) & SPI_BUSY))
-			return 0;
-	} while (!stopwatch_expired(&sw));
-
-	return -1;
-}
-
-static int execute_command(void)
-{
-	dump_state("Before Execute");
-
-	spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE);
-
-	if (wait_for_ready())
-		printk(BIOS_DEBUG,
-			"FCH SPI Error: Timeout executing command\n");
-
-	dump_state("Transaction finished");
-
-	return 0;
-}
-
-void spi_init(void)
-{
-	set_spibar(lpc_get_spibase());
-}
-
-static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
-		size_t bytesout, void *din, size_t bytesin)
-{
-	size_t count;
-	uint8_t cmd;
-	uint8_t *bufin = din;
-	const uint8_t *bufout = dout;
-
-	if (SPI_DEBUG_DRIVER)
-		printk(BIOS_DEBUG, "%s(%zx, %zx)\n", __func__, bytesout,
-			bytesin);
-
-	/* First byte is cmd which cannot be sent through FIFO */
-	cmd = bufout[0];
-	bufout++;
-	bytesout--;
-
-	/*
-	 * Check if this is a write command attempting to transfer more bytes
-	 * than the controller can handle.  Iterations for writes are not
-	 * supported here because each SPI write command needs to be preceded
-	 * and followed by other SPI commands, and this sequence is controlled
-	 * by the SPI chip driver.
-	 */
-	if (bytesout + bytesin > SPI_FIFO_DEPTH) {
-		printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI"
-				" chip driver use spi_crop_chunk()?\n");
-		return -1;
-	}
-
-	if (wait_for_ready())
-		return -1;
-
-	spi_write8(SPI_CMD_CODE, cmd);
-	spi_write8(SPI_TX_BYTE_COUNT, bytesout);
-	spi_write8(SPI_RX_BYTE_COUNT, bytesin);
-
-	for (count = 0; count < bytesout; count++)
-		spi_write8(SPI_FIFO + count, bufout[count]);
-
-	if (execute_command())
-		return -1;
-
-	for (count = 0; count < bytesin; count++)
-		bufin[count] = spi_read8(SPI_FIFO + count + bytesout);
-
-	return 0;
-}
-
-int chipset_volatile_group_begin(const struct spi_flash *flash)
-{
-	return 0;
-}
-
-int chipset_volatile_group_end(const struct spi_flash *flash)
-{
-	return 0;
-}
-
-static int xfer_vectors(const struct spi_slave *slave,
-			struct spi_op vectors[], size_t count)
-{
-	return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
-}
-
-static const struct spi_ctrlr spi_ctrlr = {
-	.xfer_vector = xfer_vectors,
-	.max_xfer_size = SPI_FIFO_DEPTH,
-	.flags = SPI_CNTRLR_DEDUCT_CMD_LEN | SPI_CNTRLR_DEDUCT_OPCODE_LEN,
-};
-
-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
-	{
-		.ctrlr = &spi_ctrlr,
-		.bus_start = 0,
-		.bus_end = 0,
-	},
-};
-
-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);