diff options
| author | Marc Jones <marcjones@sysproconsulting.com> | 2020-09-10 11:12:12 -0600 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2020-10-03 03:33:25 +0000 |
| commit | c3d92f0c73c45f20d112769d4a878180b6fdfdfb (patch) | |
| tree | 0798f3fec5af86838f8488999f2ec7be7780fe36 /src | |
| parent | b20c1023d6df94044adfb86a16d869cb88ede23b (diff) | |
soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notation
Prepare for merge with cpx.
Use the C style operators instead of the ACPI1.x polish notation.
This is much easier to read and matches the cpx code.
This generates the same ASL code.
Checked with BUILD_TIMELESS on TiogaPass.
Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl index dcb6fe2af3..b2a2ebf850 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl @@ -8,10 +8,8 @@ * PIRQ routing control is in PCR ITSS region. */ -OperationRegion (ITSS, SystemMemory, - Add (PCR_ITSS_PIRQA_ROUT, - Add (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) +OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT + + CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8) Field (ITSS, ByteAcc, NoLock, Preserve) { PIRA, 8, /* PIRQA Routing Control */ |