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authorPeichao Wang <peichao.wang@bitland.corp-partner.google.com>2020-07-08 10:54:51 +0800
committerAaron Durbin <adurbin@chromium.org>2020-08-05 15:19:54 +0000
commit92887375c58349176d96071b5917434924db9a99 (patch)
treee51a29bb2de97a45efa732ed6e6f35de7679cc21 /src
parent026e940f03107cdd32b6f479134d1b61f700a3de (diff)
mb/google/vilboz: update telemetry settings for vilboz
update telemetry value for SDLE test result. BUG=b:160698427 BRANCH=None TEST=emerge-zork coreboot Change-Id: Icce57f9be2732ff79f336daa6c447a30247366cf Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/zork/variants/vilboz/overridetree.cb5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index f9b7077d01..fe39d7c377 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -18,6 +18,11 @@ chip soc/amd/picasso
# End : OPN Performance Configuration
+ register "telemetry_vddcr_vdd_slope" = "32453" #mA
+ register "telemetry_vddcr_vdd_offset" = "168"
+ register "telemetry_vddcr_soc_slope" = "22644" #mA
+ register "telemetry_vddcr_soc_offset" = "-70"
+
# USB OC pin mapping
register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1