diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-08-10 21:43:12 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-08-12 05:24:19 +0000 |
| commit | 8adaffcbed6372970f34b85177bd42bb508d03e2 (patch) | |
| tree | 2d21ff7d3347fc043f572c9d4dd091f3c59601db /src | |
| parent | e2e1f12265e8591431280c28070b452d449a0131 (diff) | |
soc/intel/common: Fix typo mistake in cache_as_ram.S
Change-Id: I14c0e87012bdbaaff50844ed097b66e2221b1e08
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index b1648e8eed..d5f5081c3c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -365,7 +365,7 @@ find_llc_subleaf: jnz find_llc_subleaf /* - * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * Set MSR 0xC91 IA32_L3_MASK_1 = 0xE/0xFE/0xFFE/0xFFFE * for 4/8/16 way of LLC */ shr $22, %ebx |