diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-15 16:01:16 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-19 05:21:50 +0200 |
| commit | 4b86314495b17f8d944e16cfb726cd665c7d22a1 (patch) | |
| tree | 74029e6cbfba3c047376a9a7f9dbca69cbdd61f2 /src | |
| parent | c6986fac7793e119ce0f10205ff185d187654448 (diff) | |
intel/broadwell: Remove old USBDEBUG backup store in CAR
Required EHCI state is maintained as a CAR_GLOBAL to have it
properly migrated.
Change-Id: I8df413bec6faae4952670710c8ac804e0331c966
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15236
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/cache_as_ram.inc | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 20ef6e9758..37d7f30a68 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -26,7 +26,6 @@ (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_LIMIT (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) -#define USBDEBUG_VAR_SIZE 36 /* sizeof(struct ehci_debug_info) */ /* Cache 4GB - MRC_SIZE_KB for MRC */ #define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) @@ -166,9 +165,6 @@ clear_mtrrs: /* Setup the stack. */ movl $(CACHE_AS_RAM_LIMIT), %eax -#if CONFIG_USBDEBUG - sub $(USBDEBUG_VAR_SIZE), %eax -#endif movl %eax, %esp /* Restore the BIST result. */ @@ -193,15 +189,6 @@ before_romstage: post_code(0x2f) - /* Copy global variable space (for USBDEBUG) to memory */ -#if CONFIG_USBDEBUG - cld - movl $(CACHE_AS_RAM_LIMIT - USBDEBUG_VAR_SIZE), %esi - movl $(CONFIG_RAMTOP - USBDEBUG_VAR_SIZE), %edi - movl $USBDEBUG_VAR_SIZE, %ecx - rep movsb -#endif - post_code(0x30) /* Disable cache. */ |