diff options
| author | Jeremy Soller <jeremy@system76.com> | 2019-02-20 16:36:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-22 11:08:21 +0000 |
| commit | 4185de5ff7cea3007af52fdcdd7a8f4220468be1 (patch) | |
| tree | f36165a1941a48c63cdbaddfe451034a5fd52f82 /src | |
| parent | eb503296fcd4f6e2afbf2bebda63da23354058b0 (diff) | |
soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree
Tested on system76 galp3-c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d
Reviewed-on: https://review.coreboot.org/c/31535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 1f26f1e146..ab7c765043 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -162,6 +162,8 @@ struct soc_intel_cannonlake_config { uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* Enable/Disable HotPlug support for Root Port */ + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a198f1bfec..17a014b97e 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -188,6 +188,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(config->PcieClkSrcClkReq)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(config->PcieRpHotPlug)); /* eMMC and SD */ dev = dev_find_slot(0, PCH_DEVFN_EMMC); |