diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2018-11-19 12:29:51 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-23 14:56:16 +0000 |
| commit | 01f96d78ffdcf5b60079c5804ca99076cbda5d95 (patch) | |
| tree | 857dd94a3875e7ed2e0d147cf1764c1076681e88 /src | |
| parent | 6f86ff3ac85beefe73026b58ddcbe9f54be6ea46 (diff) | |
mb/intel/icelake_rvp: Enable dptf functionality
Enable dptf functionality for IceLake based U and Y systems.
Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 0d2ea76f9a..6d7fad7623 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -157,6 +157,9 @@ chip soc/intel/icelake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 62c7a828be..0972c29e12 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -157,6 +157,9 @@ chip soc/intel/icelake # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" |