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authorMartin Roth <martinroth@chromium.org>2021-04-16 11:36:01 -0600
committerMartin Roth <martinroth@google.com>2021-04-26 02:30:21 +0000
commitfdad5ad74baea3f29495126c31159a9bcb352d79 (patch)
tree5520346a1a3e7f9e7c3591581c236f3fde0d25d2 /src
parent564413246d7b7ad3972ed5f7d2ba1bb284d3b9ee (diff)
soc/amd/cezanne & picasso: Add Kconfig for hardcoded Soft Fuse bits
Currently, some of the PSP Soft Fuse bits are hardcoded in the Cezanne and Picasso makefiles. This makes it impossible for platforms to change them. This change puts the hardcoded bits in Kconfig, allowing them to be modified by the platform. BUG=b:185514903 TEST=Verify that the correct Soft Fuse bits are set. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I190ebf47cb7ae46983733dc6541776bf19a2382f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52422 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/cezanne/Kconfig14
-rw-r--r--src/soc/amd/cezanne/Makefile.inc7
-rw-r--r--src/soc/amd/picasso/Kconfig11
-rw-r--r--src/soc/amd/picasso/Makefile.inc6
4 files changed, 33 insertions, 5 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index a8d025197d..76fa2b20bc 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -321,6 +321,20 @@ config PSP_WHITELIST_FILE
depends on HAVE_PSP_WHITELIST_FILE
default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin"
+config PSP_SOFTFUSE_BITS
+ string "PSP Soft Fuse bits to enable"
+ default "28 6"
+ help
+ Space separated list of Soft Fuse bits to enable.
+ Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
+ Bit 7: Disable PSP postcodes on Renoir and newer chips only
+ (Set by PSP_DISABLE_PORT80)
+ Bit 15: PSP post code destination: 0=LPC 1=eSPI
+ (Set by PSP_INITIALIZE_ESPI)
+ Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW)
+
+ See #55758 (NDA) for additional bit definitions.
+
endmenu
config VBOOT
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 1264a249d3..f5cbcaebd0 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -101,6 +101,9 @@ else
PSP_SOFTFUSE_BITS += 29
endif
+# Use additional Soft Fuse bits specified in Kconfig
+PSP_SOFTFUSE_BITS += $(CONFIG_PSP_SOFTFUSE_BITS)
+
# type = 0x3a
ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
@@ -127,10 +130,8 @@ PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | a
APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h)
APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h)
-# type = 0xb - See #55758 (NDA) for bit definitions.
-PSP_SOFTFUSE_BITS += 28 6
-
# Helper function to return a value with given bit set
+# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions.
set-bit=$(call int-shift-left, 1 $(call _toint,$1))
PSP_SOFTFUSE=$(shell A=$(call int-add, \
$(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A)
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 63fa0103ac..fe09e111bf 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -425,6 +425,17 @@ config PSP_VERSTAGE_SIGNING_TOKEN
help
Add psp_verstage signature token to the build & PSP Directory Table
+config PSP_SOFTFUSE_BITS
+ string "PSP Soft Fuse bits to enable"
+ default "28"
+ help
+ Space separated list of Soft Fuse bits to enable.
+ Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
+ Bit 15: PSP post code destination: 0=LPC 1=eSPI
+ Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW)
+
+ See #55758 (NDA) for additional bit definitions.
+
endmenu
config VBOOT
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index e8ee087b7b..081a65fac2 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -107,6 +107,9 @@ else
PSP_SOFTFUSE_BITS += 29
endif
+# Use additional Soft Fuse bits specified in Kconfig
+PSP_SOFTFUSE_BITS += $(CONFIG_PSP_SOFTFUSE_BITS)
+
ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y)
OPT_PSP_LOAD_S0I3_FW="--load-s0i3"
endif
@@ -147,10 +150,9 @@ PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN))
endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK
-# type = 0xb - See #55758 (NDA) for bit definitions.
-PSP_SOFTFUSE_BITS += 28
# Helper function to return a value with given bit set
+# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions.
set-bit=$(call int-shift-left, 1 $(call _toint,$1))
PSP_SOFTFUSE=$(shell A=$(call int-add, \
$(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A)