mb/intel/coffeelake_rvp: Add whiskey lake rvp

Add new mainboard variant of whiskey lake rvp, which is primary
validation platform for whiskey lake silicon, support socket DDR4 memory
module.

BUG=N/A
TEST=Build and flash, confirm boot up into kernel on whiskey lake rvp
platform.

Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

6 files changed, 165 insertions, 10 deletions

diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig
index 49fba665ea..311f6d119a 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COFFEELAKE_RVP11
+if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -22,6 +22,7 @@ config VARIANT_DIR
 	string
 	default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU
 	default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11
+	default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP
 
 config MAINBOARD_PART_NUMBER
 	string
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name
index 14bd22a2e9..f9f82a223a 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name
@@ -4,3 +4,5 @@ config BOARD_INTEL_COFFEELAKE_RVPU
 	bool "-> Coffeelake U SO-DIMM DDR4 RVP"
 config BOARD_INTEL_COFFEELAKE_RVP11
 	bool "-> Coffeelake H SO-DIMM DDR4 RVP11"
+config BOARD_INTEL_WHISKEYLAKE_RVP
+	bool "-> Whiskeylake U DDR4 RVP"
diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c
index 1ea353725a..1ab2d78b5a 100644
--- a/src/mainboard/intel/coffeelake_rvp/romstage.c
+++ b/src/mainboard/intel/coffeelake_rvp/romstage.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2016 Google Inc.
- * Copyright (C) 2017-20188 Intel Corp.
+ * Copyright (C) 2017-2018 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
index dd7369b672..821cba3140 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
@@ -17,7 +17,6 @@
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
 
-#if IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)
 static const struct pad_config gpio_table[] = {
 	/* GPPC */
 	/* A0  : RCINB_TIME_SYNC_1 */
@@ -284,15 +283,8 @@ static const struct pad_config gpio_table[] = {
 	/* GPD-9  : SLP_WLANB */
 	/* GPD-10 : SLP_5B */
 	/* GPD_11 : LANPHYPC */
-
-};
-#elif IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVP11)
-static const struct pad_config gpio_table[] = {
-
 };
 
-#endif
-
 /* Early pad configuration in bootblock */
 static const struct pad_config early_gpio_table[] = {
 
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
new file mode 100644
index 0000000000..62a6635e0a
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
@@ -0,0 +1,139 @@
+chip soc/intel/cannonlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# FSP configuration
+	register "SaGv" = "3"
+	register "SmbusEnable" = "1"
+	register "ScsEmmcEnabled" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+	register "ScsSdCardEnabled" = "1"
+	register "HeciEnabled" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+
+	register "SataEnable" = "1"
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsEnable[3]" = "1"
+	register "SataPortsEnable[4]" = "1"
+	register "SataPortsEnable[5]" = "1"
+	register "SataPortsEnable[6]" = "1"
+	register "SataPortsEnable[7]" = "1"
+
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkHda" = "1"
+
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[3]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpEnable[6]" = "1"
+	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpEnable[9]" = "1"
+	register "PcieRpEnable[10]" = "1"
+	register "PcieRpEnable[11]" = "1"
+	register "PcieRpEnable[12]" = "1"
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpEnable[15]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "1"
+	register "PcieClkSrcUsage[1]" = "8"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
+	register "PcieClkSrcUsage[3]" = "13"
+	register "PcieClkSrcUsage[4]" = "4"
+	register "PcieClkSrcUsage[5]" = "14"
+
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.3 on  end # CNVi wifi
+		device pci 14.5 on  end # SDCard
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 on  end # SATA
+		device pci 19.0 on  end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 on  end # eMMC
+		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
+		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC Interface
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h
new file mode 100644
index 0000000000..c34a9b3cd9
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#endif /* __MAINBOARD_GPIO_H__ */