diff options
| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2022-09-23 14:25:41 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-28 21:29:59 +0000 |
| commit | cfec5ddc1605d0cb91449e556d2064f27b42adc0 (patch) | |
| tree | ad53d5c24b39a1b109ba21e0aefa34e69e56451c /src | |
| parent | 4236e2a23a0ad0dffc98322d961e65719158738f (diff) | |
mb/google/skyrim: Rename pcie_gpio_table to romstage_gpio_table
Rename so table more indicative of when GPIOs are set, and so it can
be used for more than just setting PCIe GPIOs.
Rename the getter function to match.
Change-Id: I285602209072247895c2cb0830f3faf675328757
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
3 files changed, 9 insertions, 8 deletions
diff --git a/src/mainboard/google/skyrim/romstage.c b/src/mainboard/google/skyrim/romstage.c index fe5b6760e4..cf93fc5685 100644 --- a/src/mainboard/google/skyrim/romstage.c +++ b/src/mainboard/google/skyrim/romstage.c @@ -9,7 +9,7 @@ void mb_pre_fspm(FSP_M_CONFIG *mcfg) const struct soc_amd_gpio *base_gpios; /* Initialize PCIe reset. */ - variant_pcie_gpio_table(&base_gpios, &base_num_gpios); + variant_romstage_gpio_table(&base_gpios, &base_num_gpios); gpio_configure_pads(base_gpios, base_num_gpios); } diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index 1a9e5d1ffe..b234a5dee3 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -188,8 +188,9 @@ static const struct soc_amd_gpio early_gpio_table[] = { PAD_GPO(GPIO_9, HIGH), }; -/* PCIE_RST needs to be brought high before FSP-M runs */ -static const struct soc_amd_gpio pcie_gpio_table[] = { +/* Romstage GPIO configuration */ +static const struct soc_amd_gpio romstage_gpio_table[] = { + /* PCIE_RST needs to be brought high before FSP-M runs */ /* Deassert all AUX_RESET lines & PCIE_RST */ /* WLAN_AUX_RESET_L (ACTIVE LOW) */ PAD_GPO(GPIO_7, HIGH), @@ -201,10 +202,10 @@ static const struct soc_amd_gpio pcie_gpio_table[] = { PAD_GPO(GPIO_6, HIGH), }; -__weak void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +__weak void variant_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { - *size = ARRAY_SIZE(pcie_gpio_table); - *gpio = pcie_gpio_table; + *size = ARRAY_SIZE(romstage_gpio_table); + *gpio = romstage_gpio_table; } void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h index 5acf96e07b..73ccc03991 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -38,7 +38,7 @@ void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); /* This function provides GPIO settings for TPM i2c bus. */ void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); -/* This function provides GPIO settings before PCIe enumeration. */ -void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* This function provides GPIO settings in romstage. */ +void variant_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); #endif /* __BASEBOARD_VARIANTS_H__ */ |