diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-08-26 15:26:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-27 08:03:47 +0100 |
| commit | 20772a84781ac69288a39c3624caebed15693025 (patch) | |
| tree | 338fb09404cf193080e30b4b6c57cc6719d633c4 /src | |
| parent | b8de44742e6334ce34499af928689d969a1a3283 (diff) | |
tegra132: Increase TrustZone Carveout Region size
Increase TZ carveout region size to 4MiB. TTB lives in the first 1MiB of the
trust zone. Rest of the TZ memory can be used by el3 monitor.
BUG=chrome-os-partner:31615
BRANCH=None
TEST=Compiles successfully and boots to kernel
Change-Id: I448574860186815992c15a358a1481faecf224bd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de0f3f8016a4e566a2bacb967ef92213648d8257
Original-Change-Id: I1f25b7b119037cba7055a1bd61997f020a0b1010
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214370
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9003
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/nvidia/tegra132/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/mmu_operations.c | 5 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/mmu_operations.h | 3 |
3 files changed, 7 insertions, 3 deletions
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 070a3ce8c7..ee50152513 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -101,7 +101,7 @@ config MTS_DIRECTORY config TRUSTZONE_CARVEOUT_SIZE_MB hex "Size of Trust Zone region" - default 0x1 + default 0x4 help Size of Trust Zone area in MiB to reserve in memory map. diff --git a/src/soc/nvidia/tegra132/mmu_operations.c b/src/soc/nvidia/tegra132/mmu_operations.c index 5e02e07f10..1f6258f02d 100644 --- a/src/soc/nvidia/tegra132/mmu_operations.c +++ b/src/soc/nvidia/tegra132/mmu_operations.c @@ -84,6 +84,7 @@ void tegra132_mmu_init(void) { uintptr_t tz_base_mib; size_t tz_size_mib; + size_t ttb_size_mib; struct memranges *map = &t132_mmap_ranges; tegra132_memrange_init(map); @@ -92,7 +93,7 @@ void tegra132_mmu_init(void) /* Place page tables at the base of the trust zone region. */ carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); tz_base_mib *= MiB; - tz_size_mib *= MiB; - mmu_init(map, (void *)tz_base_mib, tz_size_mib); + ttb_size_mib = TTB_SIZE * MiB; + mmu_init(map, (void *)tz_base_mib, ttb_size_mib); mmu_enable(tz_base_mib); } diff --git a/src/soc/nvidia/tegra132/mmu_operations.h b/src/soc/nvidia/tegra132/mmu_operations.h index bc2773ce21..8c82b26477 100644 --- a/src/soc/nvidia/tegra132/mmu_operations.h +++ b/src/soc/nvidia/tegra132/mmu_operations.h @@ -22,4 +22,7 @@ void tegra132_mmu_init(void); +/* Default ttb size of 1MiB */ +#define TTB_SIZE 0x1 + #endif //__SOC_NVIDIA_TEGRA132_MMU_OPERATIONS_H__ |