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authorArthur Heymans <arthur@aheymans.xyz>2022-05-25 14:51:50 +0200
committerPaul Fagerburg <pfagerburg@chromium.org>2022-06-02 15:58:34 +0000
commit0024678d17586aa294684e2b27acf5c04b22fb08 (patch)
tree6637a4d363ccedb0234d3aec4389f602281fe31d /src
parent346db92f8c6e42529af6dbcf34caf9c3fb1a5a12 (diff)
cpu/intel/model_fxx: Select SSE2
Starting from Intel Pentium 4, cpus featured SSE2. This will be used in the follow-up patches to determine whether to use mfence as this instruction was introduced with the SSE2 feature set. Change-Id: I8ce37d855cf84a9fb9fe9e18d77b0c19be261407 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/model_f2x/Kconfig1
-rw-r--r--src/cpu/intel/model_f3x/Kconfig1
-rw-r--r--src/cpu/intel/model_f4x/Kconfig1
3 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig
index 672cf75517..eb11a3338d 100644
--- a/src/cpu/intel/model_f2x/Kconfig
+++ b/src/cpu/intel/model_f2x/Kconfig
@@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_F2X
select SUPPORT_CPU_UCODE_IN_CBFS
select SMM_ASEG
select CPU_INTEL_COMMON
+ select SSE2
diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig
index b0a9f7ce64..ca76929dc5 100644
--- a/src/cpu/intel/model_f3x/Kconfig
+++ b/src/cpu/intel/model_f3x/Kconfig
@@ -3,3 +3,4 @@ config CPU_INTEL_MODEL_F3X
select ARCH_X86
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
+ select SSE2
diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig
index 550a978e85..a77a14c72f 100644
--- a/src/cpu/intel/model_f4x/Kconfig
+++ b/src/cpu/intel/model_f4x/Kconfig
@@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_F4X
bool
select ARCH_X86
select SUPPORT_CPU_UCODE_IN_CBFS
+ select SSE2