baytrail: gpio: Add support for direct / dedicated IRQs

Add support for DirectIRQ / dedicated IRQs. This consists of up to 16
IRQs for both SCORE and SSUS banks.

BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.

Change-Id: I4b0dc6e7ae86c9f554b6e78792239234f702764c
Reviewed-on: https://chromium-review.googlesource.com/176165
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4962
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

3 files changed, 97 insertions, 3 deletions

diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h
index 8c90c89d26..154ac84390 100644
--- a/src/soc/intel/baytrail/baytrail/gpio.h
+++ b/src/soc/intel/baytrail/baytrail/gpio.h
@@ -31,6 +31,9 @@
 #define GPNCORE_PAD_BASE		(IO_BASE_ADDRESS + 0x1000)
 #define GPSSUS_PAD_BASE			(IO_BASE_ADDRESS + 0x2000)
 
+/* DIRQ registers start at pad base + 0x980 */
+#define PAD_BASE_DIRQ_OFFSET		0x980
+
 /* Pad register offset */
 #define PAD_CONF0_REG			0x0
 #define PAD_CONF1_REG			0x4
@@ -77,6 +80,12 @@
 /* config0[27] - Direct Irq En */
 #define PAD_IRQ_EN		(1 << 27)
 
+/* config0[26] - gd_tne */
+#define PAD_TNE_IRQ		(1 << 26)
+
+/* config0[25] - gd_tpe */
+#define PAD_TPE_IRQ		(1 << 25)
+
 /* config0[24] - Gd Level */
 #define PAD_LEVEL_IRQ		(1 << 24)
 #define PAD_EDGE_IRQ		(0 << 24)
@@ -169,6 +178,26 @@
 	  .use_sel   = GPIO_USE_LEGACY, \
 	  .io_sel    = GPIO_DIR_INPUT }
 
+/* Direct / dedicated IRQ input - falling-edge triggered */
+#define GPIO_DIRQ \
+	{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
+		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ, \
+	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+	  .pad_val   = PAD_VAL_INPUT_ENABLE, \
+	  .use_sel   = GPIO_USE_LEGACY, \
+	  .io_sel    = GPIO_DIR_INPUT, \
+	  .tne       = GPIO_NEDGE_ENABLE }
+
+/* Direct / dedicated IRQ input - rising-edge triggered */
+#define GPIO_DIRQ_INVERT \
+	{ .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
+		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ, \
+	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+	  .pad_val   = PAD_VAL_INPUT_ENABLE, \
+	  .use_sel   = GPIO_USE_LEGACY, \
+	  .io_sel    = GPIO_DIR_INPUT, \
+	  .tne       = GPIO_PEDGE_ENABLE }
+
 #define GPIO_OUT_LOW \
 	{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0, \
@@ -236,6 +265,9 @@
 #define GPIO_NC		GPIO_INPUT_PU_10K
 #define GPIO_DEFAULT 	GPIO_FUNC0
 
+/* 16 DirectIRQs per supported bank */
+#define GPIO_MAX_DIRQS	16
+
 struct soc_gpio_map {
 	u32 pad_conf0;
 	u32 pad_conf1;
@@ -253,6 +285,8 @@ struct soc_gpio_config {
 	const struct soc_gpio_map *ncore;
 	const struct soc_gpio_map *score;
 	const struct soc_gpio_map *ssus;
+	const u8 (*core_dirq)[GPIO_MAX_DIRQS];
+	const u8 (*sus_dirq)[GPIO_MAX_DIRQS];
 };
 
 /* Description of GPIO 'bank' ex. {ncore, score. ssus} */
diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h
index 2359d21423..f1abae77d9 100644
--- a/src/soc/intel/baytrail/baytrail/irq.h
+++ b/src/soc/intel/baytrail/baytrail/irq.h
@@ -50,9 +50,44 @@
 #define SCC_EMMC_IRQ			45
 #define SCC_SDIO_IRQ			46
 #define SCC_SD_IRQ			47
-/* The dedicated gpio irqs are active high. */
-#define GPIO_S0_DED_IRQ(slot)		(51 + (slot))
-#define GPIO_S5_DED_IRQ(slot)		(67 + (slot))
+/* GPIO direct / dedicated IRQs. */
+#define GPIO_S0_DED_IRQ_0		51
+#define GPIO_S0_DED_IRQ_1		52
+#define GPIO_S0_DED_IRQ_2		53
+#define GPIO_S0_DED_IRQ_3		54
+#define GPIO_S0_DED_IRQ_4		55
+#define GPIO_S0_DED_IRQ_5		56
+#define GPIO_S0_DED_IRQ_6		57
+#define GPIO_S0_DED_IRQ_7		58
+#define GPIO_S0_DED_IRQ_8		59
+#define GPIO_S0_DED_IRQ_9		60
+#define GPIO_S0_DED_IRQ_10		61
+#define GPIO_S0_DED_IRQ_11		62
+#define GPIO_S0_DED_IRQ_12		63
+#define GPIO_S0_DED_IRQ_13		64
+#define GPIO_S0_DED_IRQ_14		65
+#define GPIO_S0_DED_IRQ_15		66
+#define GPIO_S5_DED_IRQ_0		67
+#define GPIO_S5_DED_IRQ_1		68
+#define GPIO_S5_DED_IRQ_2		69
+#define GPIO_S5_DED_IRQ_3		70
+#define GPIO_S5_DED_IRQ_4		71
+#define GPIO_S5_DED_IRQ_5		72
+#define GPIO_S5_DED_IRQ_6		73
+#define GPIO_S5_DED_IRQ_7		74
+#define GPIO_S5_DED_IRQ_8		75
+#define GPIO_S5_DED_IRQ_9		76
+#define GPIO_S5_DED_IRQ_10		77
+#define GPIO_S5_DED_IRQ_11		78
+#define GPIO_S5_DED_IRQ_12		79
+#define GPIO_S5_DED_IRQ_13		80
+#define GPIO_S5_DED_IRQ_14		81
+#define GPIO_S5_DED_IRQ_15		82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */
+#define _GPIO_S0_DED_IRQ(slot)		GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot)		GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot)		_GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot)		_GPIO_S5_DED_IRQ(slot)
 
 /* PIC IRQ settings. */
 #define PIRQ_PIC_IRQDISABLE		0x0
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 824ed6560b..8cc7cc0c0c 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -179,6 +179,25 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
 	southcluster_smm_save_gpio_route(route_reg);
 }
 
+static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
+			const struct gpio_bank *bank)
+{
+	u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
+	u32 val;
+	int i;
+
+	/* Write all four DIRQ registers */
+	for (i=0; i<4; ++i) {
+		val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
+		      dirq[i * 4 + 1] << 8  | dirq[i * 4];
+		write32(reg + i * 4, val);
+#ifdef GPIO_DEBUG
+		printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
+			reg + i * 4, val);
+#endif
+	}
+}
+
 void setup_soc_gpios(struct soc_gpio_config *config)
 {
 	if (config) {
@@ -186,7 +205,13 @@ void setup_soc_gpios(struct soc_gpio_config *config)
 		setup_gpios(config->score, &gpscore_bank);
 		setup_gpios(config->ssus,  &gpssus_bank);
 		setup_gpio_route(config->ssus, config->score);
+
+		if (config->core_dirq)
+			setup_dirqs(*config->core_dirq, &gpscore_bank);
+		if (config->sus_dirq)
+			setup_dirqs(*config->sus_dirq, &gpssus_bank);
 	}
+
 }
 
 struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)