diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-11-24 22:30:52 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-12-05 08:14:54 +0000 |
| commit | 1a3ae36c6abcf826e9ca7b980c81a465e53deb0a (patch) | |
| tree | a8722733de86c9ed443c7056479235759d265c21 /src | |
| parent | 6c38f35da3ff908b36ba9114dce0216df0781f66 (diff) | |
mb/google/zork/var/vliboz: Add LTE_RST power sequence
Latest HW schematic add LTE_RST pin to control module power sequence.
BUG=b:173490220
BRANCH=zork
TEST=measure the waveform is meet the LTE module spec.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/zork/variants/vilboz/gpio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 6fba0e2595..c6ef161647 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -19,6 +19,8 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { /* P sensor INT */ PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), + /* LTE_RST_L */ + PAD_GPO(GPIO_89, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) |