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authorJulius Werner <jwerner@chromium.org>2016-09-23 16:07:42 -0700
committerPatrick Georgi <pgeorgi@google.com>2016-10-07 17:55:09 +0200
commit5ddecdcf328fceb75a49d6ae5229b8d01702393d (patch)
treece3e991cb7acd81cda54139aa5959553b597ca6b /src
parentba0b9abcce220958bfb1029a5e212ef12771e89b (diff)
rockchip/rk3399: Actually remove big CPU initialization from bootblock
CL:377541 was supposed to remove the big CPU cluster initialization from rkclk_init() in the bootblock and move it to a more suitable place in ramstage. Except that next to all the code cleanup I did in that patch, I seem to have forgotten to actually remove that old code. Big thanks to Nico for spotting that in the upstream coreboot review. BRANCH=gru BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I09fe948b4587536802b42329b813177439e0804f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 77f9eaf0446b22adfca79d0adf8a0ecfd93c0040 Original-Change-Id: I13dab208225b7e43ad864f2f3cf51b3c104acd4b Original-Reported-by: Nico Huber <nico.h@gmx.de> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/389236 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16769 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/rockchip/rk3399/clock.c7
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index b9de844dcb..2596853618 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -411,13 +411,6 @@ void rkclk_init(void)
rkclk_set_pll(&cru_ptr->gpll_con[0], &gpll_init_cfg);
rkclk_set_pll(&cru_ptr->cpll_con[0], &cpll_init_cfg);
- /*
- * coreboot boot from little core, but it seem if apll_b use defalut
- * 24MHz it will take a long time to enable big core, and will cause
- * a watchdog crash, so we should do apll_b initialization here
- */
- rkclk_configure_cpu(APLL_600_MHZ, true);
-
/* configure perihp aclk, hclk, pclk */
aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);