vc/amd/fsp: Add Glinda directory

Copied from Morgana - Needs to be updated.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id3175e6e6b5c7210b7c29f30e21e5a66f234c52a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

6 files changed, 816 insertions, 0 deletions

diff --git a/src/vendorcode/amd/fsp/glinda/FspUpd.h b/src/vendorcode/amd/fsp/glinda/FspUpd.h
new file mode 100644
index 0000000000..f6e4349887
--- /dev/null
+++ b/src/vendorcode/amd/fsp/glinda/FspUpd.h
@@ -0,0 +1,21 @@
+/** @file
+ *
+ * This file is _NOT_ automatically generated in coreboot!
+ *
+ */
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#ifdef EFI32
+# include <FspEas.h>
+# include <stdint.h>
+#else
+# include <fsp_h_c99.h>
+#endif
+
+#define FSPM_UPD_SIGNATURE               0x4D5F31305F444D41        /* 'AMD_01_M' */
+
+#define FSPS_UPD_SIGNATURE               0x535F31305F444D41        /* 'AMD_01_S' */
+
+#endif
diff --git a/src/vendorcode/amd/fsp/glinda/FspUsb.h b/src/vendorcode/amd/fsp/glinda/FspUsb.h
new file mode 100644
index 0000000000..c2132ebb09
--- /dev/null
+++ b/src/vendorcode/amd/fsp/glinda/FspUsb.h
@@ -0,0 +1,64 @@
+#ifndef __FSPUSB_H__
+#define __FSPUSB_H__
+
+/* TODO: Update for Glinda */
+
+#include <FspUpd.h>
+
+#define FSP_USB_STRUCT_MAJOR_VERSION	0xd
+#define FSP_USB_STRUCT_MINOR_VERSION	0xe
+
+#define USB2_PORT_COUNT 6
+#define USB3_PORT_COUNT 3
+#define USBC_COMBO_PHY_COUNT 2
+
+struct fch_usb2_phy {
+	uint8_t compdistune;		///< COMPDISTUNE
+	uint8_t pllbtune;		///< PLLBTUNE
+	uint8_t pllitune;		///< PLLITUNE
+	uint8_t pllptune;		///< PLLPTUNE
+	uint8_t sqrxtune;		///< SQRXTUNE
+	uint8_t txfslstune;		///< TXFSLSTUNE
+	uint8_t txpreempamptune;	///< TXPREEMPAMPTUNE
+	uint8_t txpreemppulsetune;	///< TXPREEMPPULSETUNE
+	uint8_t txrisetune;		///< TXRISETUNE
+	uint8_t txvreftune;		///< TXVREFTUNE
+	uint8_t txhsxvtune;		///< TXHSXVTUNE
+	uint8_t txrestune;		///< TXRESTUNE
+} __packed;
+
+struct fch_usb3_phy {
+	uint8_t tx_term_ctrl;		///< tx_term_ctrl
+	uint8_t rx_term_ctrl;		///< rx_term_ctrl
+	uint8_t tx_vboost_lvl_en;	///< TX_VBOOST_LVL_EN
+	uint8_t tx_vboost_lvl;		///< TX_VBOOST_LVL
+} __packed;
+
+#define USB0_PORT0	0
+#define USB0_PORT1	1
+#define USB0_PORT2	1
+#define USB0_PORT3	3
+#define USB1_PORT0	(0<<2)
+#define USB1_PORT1	(1<<2)
+#define USB1_PORT2	(1<<2)
+#define USB1_PORT3	(3<<2)
+
+#define USB_COMBO_PHY_MODE_USB_C	0
+#define USB_COMBO_PHY_MODE_USB_ONLY	1
+#define USB_COMBO_PHY_MODE_USB_DPM	2
+#define USB_COMBO_PHY_MODE_USB_DPP	3
+
+struct usb_phy_config {
+	uint8_t			Version_Major;                     ///< USB IP version
+	uint8_t			Version_Minor;                     ///< USB IP version
+	uint8_t			TableLength;                       ///< TableLength
+	uint8_t			Reserved0;
+	struct fch_usb2_phy	Usb2PhyPort[USB2_PORT_COUNT];      ///< USB 2.0 Driving Strength
+	struct fch_usb3_phy	Usb3PhyPort[USB3_PORT_COUNT];      ///< USB3 PHY Adjustment
+	uint8_t			BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
+	uint8_t			PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
+	uint8_t			ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
+	uint8_t			Reserved2[4];
+} __packed;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/glinda/FspmUpd.h b/src/vendorcode/amd/fsp/glinda/FspmUpd.h
new file mode 100644
index 0000000000..eb27f5e455
--- /dev/null
+++ b/src/vendorcode/amd/fsp/glinda/FspmUpd.h
@@ -0,0 +1,117 @@
+/** @file
+ *
+ * This file is _NOT_ automatically generated in coreboot!
+ *
+ */
+
+/* TODO: Update for Glinda */
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+#include <FspUsb.h>
+
+#define FSPM_UPD_DXIO_DESCRIPTOR_COUNT	14
+#define FSPM_UPD_DDI_DESCRIPTOR_COUNT	5
+
+/** Fsp M Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0040**/	uint32_t                    bert_size;
+	/** Offset 0x0044**/	uint32_t                    tseg_size;
+	/** Offset 0x0048**/	uint32_t                    pci_express_base_addr;
+	/** Offset 0x004C**/	uint8_t                     misc_reserved[32];
+	/** Offset 0x006C**/	uint32_t                    serial_port_base;
+	/** Offset 0x0070**/	uint32_t                    serial_port_use_mmio;
+	/** Offset 0x0074**/	uint32_t                    serial_port_baudrate;
+	/** Offset 0x0078**/	uint32_t                    serial_port_refclk;
+	/** Offset 0x007C**/	uint32_t                    serial_reserved;
+	/** Offset 0x0080**/	uint8_t                     dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52];
+	/** Offset 0x0358**/	uint8_t                     fsp_owns_pcie_resets;
+	/** Offset 0x0359**/	uint8_t                     pcie_reserved[51];
+	/** Offset 0x038C**/	uint32_t                    ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT];
+	/** Offset 0x03A0**/	uint8_t                     ddi_reserved[6];
+	/** Offset 0x03A6**/	uint8_t                     ccx_down_core_mode;
+	/** Offset 0x03A7**/	uint8_t                     ccx_disable_smt;
+	/** Offset 0x03A8**/	uint8_t                     ccx_reserved[32];
+	/** Offset 0x03C8**/	uint8_t                     stt_control;
+	/** Offset 0x03C9**/	uint8_t                     stt_pcb_sensor_count;
+	/** Offset 0x03CA**/	uint16_t                    stt_min_limit;
+	/** Offset 0x03CC**/	uint16_t                    stt_m1;
+	/** Offset 0x03CE**/	uint16_t                    stt_m2;
+	/** Offset 0x03D0**/	uint16_t                    stt_m3;
+	/** Offset 0x03D2**/	uint16_t                    stt_m4;
+	/** Offset 0x03D4**/	uint16_t                    stt_m5;
+	/** Offset 0x03D6**/	uint16_t                    stt_m6;
+	/** Offset 0x03D8**/	uint16_t                    stt_c_apu;
+	/** Offset 0x03DA**/	uint16_t                    stt_c_gpu;
+	/** Offset 0x03DC**/	uint16_t                    stt_c_hs2;
+	/** Offset 0x03DE**/	uint16_t                    stt_alpha_apu;
+	/** Offset 0x03E0**/	uint16_t                    stt_alpha_gpu;
+	/** Offset 0x03E2**/	uint16_t                    stt_alpha_hs2;
+	/** Offset 0x03E4**/	uint16_t                    stt_skin_temp_apu;
+	/** Offset 0x03E6**/	uint16_t                    stt_skin_temp_gpu;
+	/** Offset 0x03E8**/	uint16_t                    stt_skin_temp_hs2;
+	/** Offset 0x03EA**/	uint16_t                    stt_error_coeff;
+	/** Offset 0x03EC**/	uint16_t                    stt_error_rate_coefficient;
+	/** Offset 0x03EE**/	uint8_t                     smartshift_enable;
+	/** Offset 0x03EF**/	uint32_t                    apu_only_sppt_limit;
+	/** Offset 0x03F3**/	uint32_t                    sustained_power_limit;
+	/** Offset 0x03F7**/	uint32_t                    fast_ppt_limit;
+	/** Offset 0x03FB**/	uint32_t                    slow_ppt_limit;
+	/** Offset 0x03FF**/	uint8_t                     system_configuration;
+	/** Offset 0x0400**/	uint8_t                     cppc_ctrl;
+	/** Offset 0x0401**/	uint8_t                     cppc_perf_limit_max_range;
+	/** Offset 0x0402**/	uint8_t                     cppc_perf_limit_min_range;
+	/** Offset 0x0403**/	uint8_t                     cppc_epp_max_range;
+	/** Offset 0x0404**/	uint8_t                     cppc_epp_min_range;
+	/** Offset 0x0405**/	uint8_t                     cppc_preferred_cores;
+	/** Offset 0x0406**/	uint8_t                     stapm_boost;
+	/** Offset 0x0407**/	uint32_t                    stapm_time_constant;
+	/** Offset 0x040B**/	uint32_t                    slow_ppt_time_constant;
+	/** Offset 0x040F**/	uint32_t                    thermctl_limit;
+	/** Offset 0x0413**/	uint8_t                     smu_soc_tuning_reserved[9];
+	/** Offset 0x041C**/	uint8_t                     iommu_support;
+	/** Offset 0x041D**/	uint8_t                     pspp_policy;
+	/** Offset 0x041E**/	uint8_t                     enable_nb_azalia;
+	/** Offset 0x041F**/	uint8_t                     audio_io_ctl;
+	/** Offset 0x0420**/	uint8_t                     pdm_mic_selection;
+	/** Offset 0x0421**/	uint8_t                     hda_enable;
+	/** Offset 0x0422**/	uint8_t                     nbio_reserved[31];
+	/** Offset 0x0441**/	uint32_t                    emmc0_mode;
+	/** Offset 0x0445**/	uint16_t                    emmc0_init_khz_preset;
+	/** Offset 0x0447**/	uint8_t                     emmc0_sdr104_hs400_driver_strength;
+	/** Offset 0x0448**/	uint8_t                     emmc0_ddr50_driver_strength;
+	/** Offset 0x0449**/	uint8_t                     emmc0_sdr50_driver_strength;
+	/** Offset 0x044A**/	uint8_t                     UnusedUpdSpace0[85];
+	/** Offset 0x049F**/	uint32_t                    gnb_ioapic_base;
+	/** Offset 0x04A3**/	uint8_t                     gnb_ioapic_id;
+	/** Offset 0x04A4**/	uint8_t                     fch_ioapic_id;
+	/** Offset 0x04A5**/	uint8_t                     sata_enable;
+	/** Offset 0x04A6**/	uint8_t                     fch_reserved[32];
+	/** Offset 0x04C6**/	uint8_t                     s0i3_enable;
+	/** Offset 0x04C7**/	uint32_t                    telemetry_vddcrvddfull_scale_current;
+	/** Offset 0x04CB**/	uint32_t                    telemetry_vddcrvddoffset;
+	/** Offset 0x04CF**/	uint32_t                    telemetry_vddcrsocfull_scale_current;
+	/** Offset 0x04D3**/	uint32_t                    telemetry_vddcrsocOffset;
+	/** Offset 0x04D7**/	uint8_t                     UnusedUpdSpace1;
+	/** Offset 0x04D8**/	struct usb_phy_config       *usb_phy;
+	/** Offset 0x04DC**/	uint8_t                     UnusedUpdSpace2[292];
+	/** Offset 0x0600**/	uint16_t                    UpdTerminator;
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0000**/	FSP_UPD_HEADER              FspUpdHeader;
+	/** Offset 0x0020**/	FSPM_ARCH_UPD               FspmArchUpd;
+	/** Offset 0x0040**/	FSP_M_CONFIG                FspmConfig;
+} FSPM_UPD;
+
+#define IMAGE_REVISION_MAJOR_VERSION 0x01
+#define IMAGE_REVISION_MINOR_VERSION 0x00
+#define IMAGE_REVISION_REVISION 0x05
+#define IMAGE_REVISION_BUILD_NUMBER 0x00
+
+#endif
diff --git a/src/vendorcode/amd/fsp/glinda/FspsUpd.h b/src/vendorcode/amd/fsp/glinda/FspsUpd.h
new file mode 100644
index 0000000000..bff5e06577
--- /dev/null
+++ b/src/vendorcode/amd/fsp/glinda/FspsUpd.h
@@ -0,0 +1,26 @@
+/** @file
+ *
+ * This file is _NOT_ automatically generated in coreboot!
+ *
+ */
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+typedef struct __packed {
+	/** Offset 0x0020**/	uint32_t                    vbios_buffer;
+	/** Offset 0x0024**/	uint64_t                    gop_reserved;
+	/** Offset 0x002C**/	uint32_t                    reserved1;
+	/** Offset 0x0030**/	uint16_t                    UpdTerminator;
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0000**/	FSP_UPD_HEADER              FspUpdHeader;
+	/** Offset 0x0020**/	FSP_S_CONFIG                FspsConfig;
+} FSPS_UPD;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/glinda/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/glinda/include/bl_uapp/bl_syscall_public.h
new file mode 100644
index 0000000000..0516e6315d
--- /dev/null
+++ b/src/vendorcode/amd/fsp/glinda/include/bl_uapp/bl_syscall_public.h
@@ -0,0 +1,377 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2022, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+/* TODO: Update for Glinda */
+
+#ifndef _BL_SYSCALL_PUBLIC_H_
+#define _BL_SYSCALL_PUBLIC_H_
+
+#include <stdint.h>
+
+#define SVC_EXIT		0x00
+#define SVC_ENTER		0x02
+#define SVC_VERSTAGE_CMD	0x3A
+
+enum verstage_cmd_id {
+	CMD_SHA	= 1,
+	CMD_MODEXP,
+	CMD_DEBUG_PRINT,
+	CMD_DEBUG_PRINT_EX,
+	CMD_UPDATE_PSP_BIOS_DIR,
+	CMD_GET_SPI_INFO,
+	CMD_MAP_SPIROM_DEVICE,
+	CMD_UNMAP_SPIROM_DEVICE,
+	CMD_READ_TIMER_VAL,
+	CMD_DELAY_IN_MICRO_SECONDS,
+	CMD_RESET_SYSTEM,
+	CMD_GET_BOOT_MODE,
+	CMD_COPY_DATA_FROM_UAPP,
+	CMD_MAP_FCH_IO_DEVICE,
+	CMD_UNMAP_FCH_IO_DEVICE,
+	CMD_CCP_DMA,
+	CMD_SET_PLATFORM_BOOT_MODE,
+	CMD_SET_FW_HASH_TABLE,
+};
+
+struct mod_exp_params {
+	char		*pExponent;	// Exponent address
+	unsigned int	ExpSize;	// Exponent size in bytes
+	char		*pModulus;	// Modulus address
+	unsigned int	ModulusSize;	// Modulus size in bytes
+	char		*pMessage;	// Message address, same size as ModulusSize
+	char		*pOutput;	// Output address; Must be big enough to hold the
+					// data of ModulusSize
+};
+
+enum psp_boot_mode {
+	PSP_BOOT_MODE_S0 = 0x0,
+	PSP_BOOT_MODE_S0i3_RESUME = 0x1,
+	PSP_BOOT_MODE_S3_RESUME = 0x2,
+	PSP_BOOT_MODE_S4 = 0x3,
+	PSP_BOOT_MODE_S5_COLD = 0x4,
+	PSP_BOOT_MODE_S5_WARM = 0x5,
+};
+
+enum reset_type
+{
+	RESET_TYPE_COLD    = 0,
+	RESET_TYPE_WARM    = 1,
+	RESET_TYPE_MAX     = 2,
+};
+
+enum fch_io_device {
+	FCH_IO_DEVICE_SPI,
+	FCH_IO_DEVICE_I2C,
+	FCH_IO_DEVICE_GPIO,
+	FCH_IO_DEVICE_ESPI,
+	FCH_IO_DEVICE_IOMUX,
+	FCH_IO_DEVICE_MISC,
+	FCH_IO_DEVICE_AOAC,
+	FCH_IO_DEVICE_IOPORT,
+	FCH_IO_DEVICE_END,
+};
+
+enum fch_i2c_controller_id {
+	FCH_I2C_CONTROLLER_ID_0 = 0,
+	FCH_I2C_CONTROLLER_ID_1 = 1,
+	FCH_I2C_CONTROLLER_ID_2 = 2,
+	FCH_I2C_CONTROLLER_ID_3 = 3,
+	FCH_I2C_CONTROLLER_ID_MAX,
+};
+
+struct spirom_info {
+	void *SpiBiosSysHubBase;
+	void *SpiBiosSmnBase;
+	uint32_t SpiBiosSize;
+};
+
+enum psp_timer_type {
+	PSP_TIMER_TYPE_CHRONO     = 0,
+	PSP_TIMER_TYPE_SECURE_RTC = 1,
+	PSP_TIMER_TYPE_MAX        = 2,
+};
+
+/* SHA types same as ccp SHA type in crypto.h */
+enum sha_type {
+	SHA_TYPE_256,
+	SHA_TYPE_384
+};
+
+/* All SHA operation supported */
+enum sha_operation_mode {
+	SHA_GENERIC
+};
+
+/* SHA Supported Data Structures */
+struct sha_generic_data {
+	enum sha_type	SHAType;
+	uint8_t		*Data;
+	uint32_t	DataLen;
+	uint32_t	DataMemType;
+	uint8_t		*Digest;
+	uint32_t	DigestLen;
+	uint8_t		*IntermediateDigest;
+	uint32_t	IntermediateMsgLen;
+	uint32_t	Init;
+	uint32_t	Eom;
+};
+
+/*
+ * This is state that PSP manages internally.
+ * We only report BOOT_MODE_DEVELOPER or BOOT_MODE_NORMAL in verstage.
+ */
+enum chrome_platform_boot_mode
+{
+	NON_CHROME_BOOK_BOOT_MODE                = 0x0,
+	CHROME_BOOK_BOOT_MODE_UNSIGNED_VERSTAGE  = 0x1,
+	CHROME_BOOK_BOOT_MODE_NORMAL             = 0x2,
+	CHROME_BOOK_BOOT_MODE_DEVELOPER          = 0x3,
+	CHROME_BOOK_BOOT_MODE_TYPE_MAX_LIMIT     = 0x4, // used for boundary check
+};
+
+struct psp_fw_entry_hash_256 {
+	uint16_t fw_type;
+	uint16_t sub_type;
+	uint8_t  sha[32];
+} __packed;
+
+struct psp_fw_entry_hash_384 {
+	uint16_t fw_type;
+	uint16_t sub_type;
+	uint8_t  sha[48];
+} __packed;
+
+struct psp_fw_hash_table {
+	uint16_t version;			// Version of psp_fw_hash_table, Start with 0.
+	uint16_t no_of_entries_256;
+	uint16_t no_of_entries_384;
+	struct psp_fw_entry_hash_256 *fw_hash_256;
+	struct psp_fw_entry_hash_384 *fw_hash_384;
+} __packed;
+
+/*
+ * Exit to the main Boot Loader. This does not return back to user application.
+ *
+ * Parameters:
+ *     status  -   either Ok or error code defined by AGESA
+ */
+void svc_exit(uint32_t status);
+
+/* Print debug message into serial console.
+ *
+ * Parameters:
+ *     string     -   null-terminated string
+ */
+void svc_debug_print(const char *string);
+
+/* Print 4 DWORD values in hex to serial console
+ *
+ * Parameters:
+ *     dword0...dword3 - 32-bit DWORD to print
+ */
+void svc_debug_print_ex(uint32_t dword0,
+		uint32_t dword1, uint32_t dword2, uint32_t dword3);
+
+/* Description     - Returns the current boot mode from the enum psp_boot_mode found in
+ *                   bl_public.h.
+ *
+ * Inputs          - boot_mode - Output parameter passed in R0
+ *
+ * Outputs         - The boot mode in boot_mode.
+ *                   See Return Values.
+ *
+ * Return Values   - BL_OK
+ *                   BL_ERR_NULL_PTR
+ *                   Other BL_ERRORs lofted up from called functions
+ */
+uint32_t svc_get_boot_mode(uint32_t *boot_mode);
+
+/* Add delay in micro seconds
+ *
+ * Parameters:
+ *     delay       - required delay value in microseconds
+ *
+ * Return value: NONE
+ */
+void svc_delay_in_usec(uint32_t delay);
+
+/* Get the SPI-ROM information
+ *
+ * Parameters:
+ *     spi_rom_iInfo  - SPI-ROM information
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info);
+
+/* Map the FCH IO device register space (SPI/I2C/GPIO/eSPI/etc...)
+ *
+ * Parameters:
+ *     io_device         - ID for respective FCH IO controller register space to be mapped
+ *     arg1              - Based on IODevice ID, interpretation of this argument changes.
+ *     arg2              - Based on IODevice ID, interpretation of this argument changes.
+ *     io_device_axi_addr    - AXI address for respective FCH IO device register space
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_map_fch_dev(enum fch_io_device io_device,
+		uint32_t arg1, uint32_t arg2, void **io_device_axi_addr);
+
+/* Unmap the FCH IO device register space mapped earlier using Svc_MapFchIODevice()
+ *
+ * Parameters:
+ *     io_device        - ID for respective FCH IO controller register space to be unmapped
+ *     io_device_addr   - AXI address for respective FCH IO device register space
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_unmap_fch_dev(enum fch_io_device io_device,
+		void *io_device_axi_addr);
+
+/* Map the SPIROM FLASH device address space
+ *
+ * Parameters:
+ *     SpiRomAddr     - Address in SPIROM tobe mapped (SMN based)
+ *     size           - Size to be mapped
+ *     pSpiRomAddrAxi - Mapped address in AXI space
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_map_spi_rom(void *spi_rom_addr,
+		uint32_t size, void **spi_rom_axi_addr);
+
+/* Unmap the SPIROM FLASH device address space mapped earlier using Svc_MapSpiRomDevice()
+ *
+ * Parameters:
+ *     pSpiRomAddrAxi - Address in AXI address space previously mapped
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_unmap_spi_rom(void *spi_rom_addr);
+
+/* Updates the offset at which PSP or BIOS Directory can be found in the
+ * SPI flash
+ *
+ * Parameters:
+ *     psp_dir_offset - [in/out] Offset at which PSP Directory can be
+ *                      found in the SPI Flash. Same pointer is used
+ *                      to return the offset in case of GET operation
+ *     bios_dir_offset - [in/out] Offset at which BIOS Directory can be
+ *                       found in the SPI Flash. Same pointer is used
+ *                       to return the offset in case of GET operation
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset,
+		uint32_t *bios_dir_offset);
+
+/* Copies the data that is shared by verstage to the PSP BL owned memory
+ *
+ * Parameters:
+ *     address - Address in UAPP controlled/owned memory
+ *     size    - Total size of memory to copy (max 16Kbytes)
+ */
+uint32_t svc_save_uapp_data(void *address, uint32_t size);
+
+/*
+ *    Read timer raw (currently CHRONO and RTC) value
+ *
+ *    Parameters:
+ *                type            - [in] Type of timer UAPP would like to read from
+ *                                  (currently CHRONO and RTC)
+ *                counter_value   - [out] return the raw counter value read from
+ *                                  RTC or CHRONO_LO/HI counter register
+ -----------------------------------------------------------------------------*/
+uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value);
+
+/*
+ *    Reset the system
+ *
+ *   Parameters:
+ *      reset_type -   Cold or Warm reset
+ */
+uint32_t svc_reset_system(enum reset_type reset_type);
+
+/*
+ *    Write postcode to Port-80
+ *
+ *    Parameters:
+ *                postcode -   Postcode value to be written on port-80h
+ */
+uint32_t svc_write_postcode(uint32_t postcode);
+
+/*
+ * Generic SHA call for SHA, SHA_OTP, SHA_HMAC
+ */
+uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode);
+
+/*
+ * Calculate ModEx
+ *
+ * Parameters:
+ *       mod_exp_param - ModExp parameters
+ *
+ *   Return value: BL_OK or error code
+ */
+uint32_t svc_modexp(struct mod_exp_params *mod_exp_param);
+
+/*
+ * Copies the data from source to destination using ccp
+ *
+ * Parameters:
+ *   Source Address - SPI ROM offset
+ *   Destination Address - Address in Verstage memory
+ *   Size    - Total size to copy
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size);
+
+/*
+ * Get the Platform boot mode from verstage. Normal or developer
+ *
+ * Parameters:
+ *       - boot mode
+ -----------------------------------------------------------------------------*/
+uint32_t svc_set_platform_boot_mode(enum chrome_platform_boot_mode boot_mode);
+
+/*
+ * Set the PSP FW hash table.
+ *
+ * Parameters:
+ *       - hash_table - Table of hash for each PSP binary signed against SoC chain of trust
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_set_fw_hash_table(struct psp_fw_hash_table *hash_table);
+
+/* C entry point for the Bootloader Userspace Application */
+void Main(void);
+
+#endif /* _BL_SYSCALL__PUBLIC_H_ */
diff --git a/src/vendorcode/amd/fsp/glinda/platform_descriptors.h b/src/vendorcode/amd/fsp/glinda/platform_descriptors.h
new file mode 100644
index 0000000000..998534a6a1
--- /dev/null
+++ b/src/vendorcode/amd/fsp/glinda/platform_descriptors.h
@@ -0,0 +1,211 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * These definitions are used to describe PCIe bifurcation and display physical
+ * connector types connected to the SOC.
+ */
+
+/* TODO: Update for Glinda */
+
+#ifndef PI_PLATFORM_DESCRIPTORS_H
+#define PI_PLATFORM_DESCRIPTORS_H
+
+#define NUM_DXIO_PHY_PARAMS	6
+#define NUM_DXIO_PORT_PARAMS	6
+
+/* Engine descriptor type */
+enum dxio_engine_type {
+	UNUSED_ENGINE	= 0x00,	// Unused descriptor
+	PCIE_ENGINE	= 0x01,	// PCIe port
+	USB_ENGINE	= 0x02,	// USB port
+	SATA_ENGINE	= 0x03,	// SATA
+	DP_ENGINE	= 0x08,	// Digital Display
+	ETHERNET_ENGINE	= 0x10,	// Ethernet (GBe, XGBe)
+	MAX_ENGINE		// Max engine type for boundary check.
+};
+
+/* PCIe link capability/speed */
+enum dxio_link_speed_cap {
+	GEN_MAX = 0,		// Maximum supported
+	GEN1,
+	GEN2,
+	GEN3,
+	GEN_INVALID		// Max Gen for boundary check
+};
+
+/* Upstream Auto Speed Change Allowed */
+enum dxio_upstream_auto_speed_change {
+	SPDC_DEFAULT = 0,      // Enabled for Gen2 and Gen3
+	SPDC_DISABLED,
+	SPDC_ENABLED,
+	SPDC_INVALID
+};
+
+/* SATA ChannelType initialization */
+enum dxio_sata_channel_type {
+	SATA_CHANNEL_OTHER = 0,	// Default Channel Type
+	SATA_CHANNEL_SHORT,	// Short Trace Channel Type
+	SATA_CHANNEL_LONG	// Long Trace Channel Type
+};
+
+/* CLKREQ for PCIe type descriptors */
+enum cpm_clk_req {
+	CLK_DISABLE = 0x00,
+	CLK_REQ0,
+	CLK_REQ1,
+	CLK_REQ2,
+	CLK_REQ3,
+	CLK_REQ4_GFX,
+	CLK_REQ5,
+	CLK_REQ6,
+	CLK_ENABLE = 0xff,
+};
+
+/* PCIe link ASPM initialization */
+enum dxio_aspm_type {
+	ASPM_DISABLED = 0,	// Disabled
+	ASPM_L0s,		// PCIe L0s link state
+	ASPM_L1,		// PCIe L1 link state
+	ASPM_L0sL1,		// PCIe L0s & L1 link state
+	ASPM_MAX		// Not valid value, used to verify input
+};
+
+enum dxio_port_param_type {
+	PP_DEVICE = 1,
+	PP_FUNCTION,
+	PP_PORT_PRESENT,
+	PP_LINK_SPEED_CAP,
+	PP_LINK_ASPM,
+	PP_HOTPLUG_TYPE,
+	PP_CLKREQ,
+	PP_ASPM_L1_1,
+	PP_ASPM_L1_2,
+	PP_COMPLIANCE,
+	PP_SAFE_MODE,
+	PP_CHIPSET_LINK,
+	PP_CLOCK_PM,
+	PP_CHANNELTYPE,
+	PP_TURN_OFF_UNUSED_LANES,
+	PP_APIC_GROUPMAP,
+	PP_APIC_SWIZZLE,
+	PP_APIC_BRIDGEINT,
+	PP_MASTER_PLL,
+	PP_SLOT_NUM,
+	PP_PHY_PARAM,
+	PP_ESM,
+	PP_CCIX,
+	PP_GEN3_DS_TX_PRESET,
+	PP_GEN3_DS_RX_PRESET_HINT,
+	PP_GEN3_US_TX_PRESET,
+	PP_GEN3_US_RX_PRESET_HINT,
+	PP_GEN4_DS_TX_PRESET,
+	PP_GEN4_US_TX_PRESET,
+	PP_GEN3_FIXED_PRESET,
+	PP_GEN4_FIXED_PRESET,
+	PP_PSPP_DC,
+	PP_PSPP_AC,
+	PP_GEN2_DEEMPHASIS,
+	PP_INVERT_POLARITY,
+	PP_TARGET_LINK_SPEED,
+	PP_GEN4_DLF_CAP_DISABLE,
+	PP_GEN4_DLF_EXCHG_DISABLE
+};
+
+/* DDI Aux channel */
+enum ddi_aux_type {
+	DDI_AUX1 = 0,
+	DDI_AUX2,
+	DDI_AUX3,
+	DDI_AUX4,
+	DDI_AUX5,
+	DDI_AUX6,
+	DDI_AUX_MAX		// Not valid value, used to verify input
+};
+
+/* DDI Hdp Index */
+enum ddi_hdp_type {
+	DDI_HDP1 = 0,
+	DDI_HDP2,
+	DDI_HDP3,
+	DDI_HDP4,
+	DDI_HDP5,
+	DDI_HDP6,
+	DDI_HDP_MAX		// Not valid value, used to verify input
+};
+
+/* DDI display connector type */
+enum ddi_connector_type {
+	DDI_DP = 0,		// DP
+	DDI_EDP,		// eDP
+	DDI_SINGLE_LINK_DVI,	// Single Link DVI-D
+	DDI_DUAL_LINK_DVI,	// Dual Link DVI-D
+	DDI_HDMI,		// HDMI
+	DDI_DP_TO_VGA,		// DP-to-VGA
+	DDI_DP_TO_LVDS,		// DP-to-LVDS
+	DDI_NUTMEG_DP_TO_VGA,	// Hudson-2 NutMeg DP-to-VGA
+	DDI_SINGLE_LINK_DVI_I,	// Single Link DVI-I
+	DDI_CRT,		// CRT (VGA)
+	DDI_LVDS,		// LVDS
+	DDI_EDP_TO_LVDS,	// eDP-to-LVDS translator chip without AMD SW init
+	DDI_EDP_TO_LVDS_SW,	// eDP-to-LVDS translator which requires AMD SW init
+	DDI_AUTO_DETECT,	// VBIOS auto detect connector type
+	DDI_UNUSED_TYPE,	// UnusedType
+	DDI_MAX_CONNECTOR_TYPE	// Not valid value, used to verify input
+};
+
+/* Glinda DDI Descriptor: used for configuring display outputs */
+typedef struct __packed {
+	uint8_t		connector_type;	// see ddi_connector_type
+	uint8_t		aux_index;	// see ddi_aux_type
+	uint8_t		hdp_index;	// see ddi_hdp_type
+	uint8_t		reserved;
+} fsp_ddi_descriptor;
+
+/*
+ * Glinda DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
+ * bifurcation and other settings. Beware that the lane numbers in here are the
+ * logical and not the physical lane numbers!
+ *
+ * Glinda DXIO logical lane to physical PCIe lane mapping:
+ *
+ * logical | physical
+ * --------|------------
+ * [00:03] | GPP[03:00]
+ *
+ * Different ports mustn't overlap or be assigned to the same lane(s). Within
+ * ports with the same width the one with a higher start logical lane number
+ * needs to be assigned to a higher PCIe root port number; ports of the same
+ * size don't have to be assigned to consecutive PCIe root ports though.
+ */
+typedef struct __packed {
+	uint8_t		engine_type;			// See dxio_engine_type
+	uint8_t		start_logical_lane;		// Start lane of the pci device
+	uint8_t		end_logical_lane;		// End lane of the pci device
+	uint8_t		gpio_group_id;			// GPIO number used as reset
+	uint32_t	port_present		:1;	// Should be TRUE if train link
+	uint32_t	reserved_3		:7;
+	uint32_t	device_number		:5;	// Desired root port device number
+	uint32_t	function_number		:3;	// Desired root port function number
+	uint32_t	link_speed_capability	:2;	// See dxio_link_speed_cap
+	uint32_t	auto_spd_change		:2;	// See dxio_upstream_auto_speed_change
+	uint32_t	eq_preset		:4;	// Gen3 equalization preset
+	uint32_t	link_aspm		:2;	// See dxio_aspm_type
+	uint32_t	link_aspm_L1_1		:1;	// En/Dis root port capabilities for L1.1
+	uint32_t	link_aspm_L1_2		:1;	// En/Dis root port capabilities for L1.2
+	uint32_t	clk_req			:4;	// See cpm_clk_req
+	uint8_t		link_hotplug;			// Currently unused by FSP
+	uint8_t		slot_power_limit;		// Currently unused by FSP
+	uint32_t	slot_power_limit_scale	:2;	// Currently unused by FSP
+	uint32_t	reserved_4		:6;
+	uint32_t	link_compliance_mode	:1;	// Currently unused by FSP
+	uint32_t	link_safe_mode		:1;	// Currently unused by FSP
+	uint32_t	sb_link			:1;	// Currently unused by FSP
+	uint32_t	clk_pm_support		:1;	// Currently unused by FSP
+	uint32_t	channel_type		:3;	// See dxio_sata_channel_type
+	uint32_t	turn_off_unused_lanes	:1;	// Power down lanes if device not present
+	uint8_t		reserved[4];
+	uint8_t		phy_params[NUM_DXIO_PHY_PARAMS*2];
+	uint16_t	port_params[NUM_DXIO_PORT_PARAMS*2];	// key-value parameters. see dxio_port_param_type
+} fsp_dxio_descriptor;
+
+#endif /* PI_PLATFORM_DESCRIPTORS_H */