vc/amd/fsp/sabrina: add as a copy of vc/amd/fsp/cezanne

The AMD Sabrina SoC will be using the FSP driver to call into the
corresponding FSP binary to do its part of for the silicon
initialization, so we need an initial set of FSP headers for the AMD
Sabrina SoC code to build. Since the FSP interface for this SoC won't be
too different from the Cezanne FSP interface, we'll start with a copy of
the Cezanne FSP headers and update/replace them as soon as the proper
FSP headers for Sabrina will be available.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib3bf50598efe60673b81cf99da491866fb5dc121
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

13 files changed, 1284 insertions, 0 deletions

diff --git a/src/vendorcode/amd/fsp/sabrina/FspGuids.h b/src/vendorcode/amd/fsp/sabrina/FspGuids.h
new file mode 100644
index 0000000000..0eca78e711
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/FspGuids.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __FSP_GUIDS__
+#define __FSP_GUIDS__
+
+#include <uuid.h>
+
+#define AMD_FSP_TSEG_HOB_GUID \
+		GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \
+		0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)
+
+#define AMD_FSP_ACPI_ALIB_HOB_GUID \
+		GUID_INIT(0x42494c41, 0x4002, 0x403b, \
+		0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A)
+
+#define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \
+		GUID_INIT(0X6D5CD69D, 0XFB24, 0X4461, \
+		0XAA, 0X32, 0X8E, 0XE1, 0XB3, 0X3, 0X31, 0X9C )
+
+#endif /* __FSP_GUIDS__ */
diff --git a/src/vendorcode/amd/fsp/sabrina/FspUpd.h b/src/vendorcode/amd/fsp/sabrina/FspUpd.h
new file mode 100644
index 0000000000..c9202cea9c
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/FspUpd.h
@@ -0,0 +1,22 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#ifdef EFI32
+# include <FspEas.h>
+# include <stdint.h>
+#else
+# include <fsp_h_c99.h>
+#endif
+
+#define FSPM_UPD_SIGNATURE               0x4d5f454e415a4543        /* 'CEZANE_M' */
+
+#define FSPS_UPD_SIGNATURE               0x535f454e415a4543        /* 'CEZANE_S' */
+
+
+#endif
diff --git a/src/vendorcode/amd/fsp/sabrina/FspUsb.h b/src/vendorcode/amd/fsp/sabrina/FspUsb.h
new file mode 100644
index 0000000000..6563cacc81
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/FspUsb.h
@@ -0,0 +1,56 @@
+#ifndef __FSPUSB_H__
+#define __FSPUSB_H__
+
+#include <FspUpd.h>
+
+#define USB2_PORT_COUNT 8
+#define USB3_PORT_COUNT 4
+#define USBC_COMBO_PHY_COUNT 2
+
+struct fch_usb2_phy {
+	uint8_t			compdstune;                             ///< COMPDSTUNE
+	uint8_t			sqrxtune;                               ///< SQRXTUNE
+	uint8_t			txfslstune;                             ///< TXFSLSTUNE
+	uint8_t			txpreempamptune;                        ///< TXPREEMPAMPTUNE
+	uint8_t			txpreemppulsetune;                      ///< TXPREEMPPULSETUNE
+	uint8_t			txrisetune;                             ///< TXRISETUNE
+	uint8_t			txvreftune;                             ///< TXVREFTUNE
+	uint8_t			txhsxvtune;                             ///< TXHSXVTUNE
+	uint8_t			txrestune;                              ///< TXRESTUNE
+} __packed;
+
+struct fch_usb3_phy {
+	uint8_t			tx_term_ctrl;                           ///< tx_term_ctrl
+	uint8_t			rx_term_ctrl;                           ///< rx_term_ctrl
+	uint8_t			tx_vboost_lvl_en;                       ///< TX_VBOOST_LVL_EN
+	uint8_t			tx_vboost_lvl;                          ///< TX_VBOOST_LVL
+} __packed;
+
+#define USB0_PORT0	0
+#define USB0_PORT1	1
+#define USB0_PORT2	1
+#define USB0_PORT3	3
+#define USB1_PORT0	(0<<2)
+#define USB1_PORT1	(1<<2)
+#define USB1_PORT2	(1<<2)
+#define USB1_PORT3	(3<<2)
+
+#define USB_COMBO_PHY_MODE_USB_C	0
+#define USB_COMBO_PHY_MODE_USB_ONLY	1
+#define USB_COMBO_PHY_MODE_USB_DPM	2
+#define USB_COMBO_PHY_MODE_USB_DPP	3
+
+struct usb_phy_config {
+	uint8_t			Version_Major;                     ///< USB IP version
+	uint8_t			Version_Minor;                     ///< USB IP version
+	uint8_t			TableLength;                       ///< TableLength
+	uint8_t			Reserved0;
+	struct fch_usb2_phy	Usb2PhyPort[USB2_PORT_COUNT];      ///< USB 2.0 Driving Strength
+	struct fch_usb3_phy	Usb3PhyPort[USB3_PORT_COUNT];      ///< USB3 PHY Adjustment
+	uint8_t			BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
+	uint8_t			PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
+	uint8_t			ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
+	uint8_t			Reserved2[4];
+} __packed;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/sabrina/FspmUpd.h b/src/vendorcode/amd/fsp/sabrina/FspmUpd.h
new file mode 100644
index 0000000000..f21ca42169
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/FspmUpd.h
@@ -0,0 +1,110 @@
+/** @file
+ *
+ * This file is _NOT_ automatically generated in coreboot!
+ *
+ */
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+#include <FspUsb.h>
+
+#define FSPM_UPD_DXIO_DESCRIPTOR_COUNT	14
+#define FSPM_UPD_DDI_DESCRIPTOR_COUNT	5
+
+/** Fsp M Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0040**/	uint32_t                    bert_size;
+	/** Offset 0x0044**/	uint32_t                    tseg_size;
+	/** Offset 0x0048**/	uint32_t                    pci_express_base_addr;
+	/** Offset 0x004C**/	uint8_t                     misc_reserved[32];
+	/** Offset 0x006C**/	uint32_t                    serial_port_base;
+	/** Offset 0x0070**/	uint32_t                    serial_port_use_mmio;
+	/** Offset 0x0074**/	uint32_t                    serial_port_baudrate;
+	/** Offset 0x0078**/	uint32_t                    serial_port_refclk;
+	/** Offset 0x007C**/	uint32_t                    serial_reserved;
+	/** Offset 0x0080**/	uint8_t                     dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52];
+	/** Offset 0x0358**/	uint8_t                     fsp_owns_pcie_resets;
+	/** Offset 0x0359**/	uint8_t                     pcie_reserved[51];
+	/** Offset 0x038C**/	uint32_t                    ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT];
+	/** Offset 0x03A0**/	uint8_t                     ddi_reserved[6];
+	/** Offset 0x03A6**/	uint8_t                     ccx_down_core_mode;
+	/** Offset 0x03A7**/	uint8_t                     ccx_disable_smt;
+	/** Offset 0x03A8**/	uint8_t                     ccx_reserved[32];
+	/** Offset 0x03C8**/	uint8_t                     stt_control;
+	/** Offset 0x03C9**/	uint8_t                     stt_pcb_sensor_count;
+	/** Offset 0x03CA**/	uint16_t                    stt_min_limit;
+	/** Offset 0x03CC**/	uint16_t                    stt_m1;
+	/** Offset 0x03CE**/	uint16_t                    stt_m2;
+	/** Offset 0x03D0**/	uint16_t                    stt_m3;
+	/** Offset 0x03D2**/	uint16_t                    stt_m4;
+	/** Offset 0x03D4**/	uint16_t                    stt_m5;
+	/** Offset 0x03D6**/	uint16_t                    stt_m6;
+	/** Offset 0x03D8**/	uint16_t                    stt_c_apu;
+	/** Offset 0x03DA**/	uint16_t                    stt_c_gpu;
+	/** Offset 0x03DC**/	uint16_t                    stt_c_hs2;
+	/** Offset 0x03DE**/	uint16_t                    stt_alpha_apu;
+	/** Offset 0x03E0**/	uint16_t                    stt_alpha_gpu;
+	/** Offset 0x03E2**/	uint16_t                    stt_alpha_hs2;
+	/** Offset 0x03E4**/	uint16_t                    stt_skin_temp_apu;
+	/** Offset 0x03E6**/	uint16_t                    stt_skin_temp_gpu;
+	/** Offset 0x03E8**/	uint16_t                    stt_skin_temp_hs2;
+	/** Offset 0x03EA**/	uint16_t                    stt_error_coeff;
+	/** Offset 0x03EC**/	uint16_t                    stt_error_rate_coefficient;
+	/** Offset 0x03EE**/	uint8_t                     smartshift_enable;
+	/** Offset 0x03EF**/	uint32_t                    apu_only_sppt_limit;
+	/** Offset 0x03F3**/	uint32_t                    sustained_power_limit;
+	/** Offset 0x03F7**/	uint32_t                    fast_ppt_limit;
+	/** Offset 0x03FB**/	uint32_t                    slow_ppt_limit;
+	/** Offset 0x03FF**/	uint8_t                     system_configuration;
+	/** Offset 0x0400**/	uint8_t                     cppc_ctrl;
+	/** Offset 0x0401**/	uint8_t                     cppc_perf_limit_max_range;
+	/** Offset 0x0402**/	uint8_t                     cppc_perf_limit_min_range;
+	/** Offset 0x0403**/	uint8_t                     cppc_epp_max_range;
+	/** Offset 0x0404**/	uint8_t                     cppc_epp_min_range;
+	/** Offset 0x0405**/	uint8_t                     cppc_preferred_cores;
+	/** Offset 0x0406**/	uint8_t                     stapm_boost;
+	/** Offset 0x0407**/	uint32_t                    stapm_time_constant;
+	/** Offset 0x040B**/	uint32_t                    slow_ppt_time_constant;
+	/** Offset 0x040F**/	uint32_t                    thermctl_limit;
+	/** Offset 0x0413**/	uint8_t                     smu_soc_tuning_reserved[9];
+	/** Offset 0x041C**/	uint8_t                     iommu_support;
+	/** Offset 0x041D**/	uint8_t                     pspp_policy;
+	/** Offset 0x041E**/	uint8_t                     enable_nb_azalia;
+	/** Offset 0x041F**/	uint8_t                     audio_io_ctl;
+	/** Offset 0x0420**/	uint8_t                     pdm_mic_selection;
+	/** Offset 0x0421**/	uint8_t                     hda_enable;
+	/** Offset 0x0422**/	uint8_t                     nbio_reserved[31];
+	/** Offset 0x0441**/	uint32_t                    emmc0_mode;
+	/** Offset 0x0445**/	uint16_t                    emmc0_init_khz_preset;
+	/** Offset 0x0447**/	uint8_t                     emmc0_sdr104_hs400_driver_strength;
+	/** Offset 0x0448**/	uint8_t                     emmc0_ddr50_driver_strength;
+	/** Offset 0x0449**/	uint8_t                     emmc0_sdr50_driver_strength;
+	/** Offset 0x044A**/	uint8_t                     UnusedUpdSpace0[85];
+	/** Offset 0x049F**/	uint32_t                    gnb_ioapic_base;
+	/** Offset 0x04A3**/	uint8_t                     gnb_ioapic_id;
+	/** Offset 0x04A4**/	uint8_t                     fch_ioapic_id;
+	/** Offset 0x04A5**/	uint8_t                     sata_enable;
+	/** Offset 0x04A6**/	uint8_t                     fch_reserved[32];
+	/** Offset 0x04C6**/	uint8_t                     s0i3_enable;
+	/** Offset 0x04C7**/	uint32_t                    telemetry_vddcrvddfull_scale_current;
+	/** Offset 0x04CB**/	uint32_t                    telemetry_vddcrvddoffset;
+	/** Offset 0x04CF**/	uint32_t                    telemetry_vddcrsocfull_scale_current;
+	/** Offset 0x04D3**/	uint32_t                    telemetry_vddcrsocOffset;
+	/** Offset 0x04D7**/	uint8_t                     UnusedUpdSpace1;
+	/** Offset 0x04D8**/	struct usb_phy_config       *usb_phy;
+	/** Offset 0x04DC**/	uint8_t                     UnusedUpdSpace2[292];
+	/** Offset 0x0600**/	uint16_t                    UpdTerminator;
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0000**/	FSP_UPD_HEADER              FspUpdHeader;
+	/** Offset 0x0020**/	FSPM_ARCH_UPD               FspmArchUpd;
+	/** Offset 0x0040**/	FSP_M_CONFIG                FspmConfig;
+} FSPM_UPD;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/sabrina/FspsUpd.h b/src/vendorcode/amd/fsp/sabrina/FspsUpd.h
new file mode 100644
index 0000000000..3ac52c097f
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/FspsUpd.h
@@ -0,0 +1,26 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+typedef struct __packed {
+	/** Offset 0x0020**/	uint32_t                    vbios_buffer;
+	/** Offset 0x0024**/	uint64_t                    gop_reserved;
+	/** Offset 0x002C**/	uint32_t                    reserved1;
+	/** Offset 0x0030**/	uint16_t                    UpdTerminator;
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct __packed {
+	/** Offset 0x0000**/	FSP_UPD_HEADER              FspUpdHeader;
+	/** Offset 0x0020**/	FSP_S_CONFIG                FspsConfig;
+} FSPS_UPD;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S
new file mode 100644
index 0000000000..40ea4111cd
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S
@@ -0,0 +1,44 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2019, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+.arm
+.global LastBytes
+.section PSP_FOOTER_DATA, "ad", %note
+.balign 64
+
+// Note: this is used for determining the size of the binary. It is 64 byte aligned and 64 byte
+//       in size so that the binary size is multiple of 64 bytes.
+//
+LastBytes:
+    .byte     0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99
+    .byte     0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99
+    .byte     0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99
+    .byte     0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99,0x99
+
+.end
diff --git a/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_header.inc b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_header.inc
new file mode 100644
index 0000000000..35c906a445
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_header.inc
@@ -0,0 +1,64 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2019, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+.global LastBytes
+
+#define BL_UAPP_START_ADDRESS	0x00036000
+#define SIZE_OF_THIS_HEADER	256
+#define SIZE_OF_PSP_END		64
+#define IMAGE_SIZE		LastBytes + SIZE_OF_PSP_END - BL_UAPP_START_ADDRESS - SIZE_OF_THIS_HEADER
+
+#define IMAGE_VERSION 		0x01,0x00,0x00,0x00
+#define FW_TYPE			0x52
+
+
+    // 256 byte binary header
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00     // nonce
+    .byte     0x00,0x00,0x00,0x00                                                                 // header version
+    .word     IMAGE_SIZE
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     IMAGE_VERSION
+    .byte     0x00,0x00,0x00,0x00                                                                 // APU Family ID
+    .byte     0x00,0x01,0x00,0x00                                                                 // Load Address
+    .byte     0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     FW_TYPE
+    .byte     0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+    .byte     0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
diff --git a/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S
new file mode 100644
index 0000000000..f5f1e18e6c
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2019, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#include <arch/asm.h>
+#include <bl_uapp/bl_errorcodes_public.h>
+
+	.global Main
+	.global _psp_vs_start
+
+	.global  PSP_VERSTAGE_STACK_END
+
+.arm
+.text
+.section "PSP_HEADER_DATA", "aw", %note
+
+//==============================================================================
+// First 256 bytes of the binary image contain the header.
+// Executable code starts from offset 0x100.
+//==============================================================================
+#include "bl_uapp_header.inc"
+
+//==============================================================================
+// This is entry point to the binary which is called by main Boot Loader.
+//==============================================================================
+
+ENTRY(_psp_vs_start)
+
+	ldr	sp, =PSP_VERSTAGE_STACK_END // stack pointer
+
+	// Return value contains Virtual Address of mapped stack
+	//
+	ldr	lr, =ShouldNotBeReached // return address
+
+	ldr	r2, =Main               // pass control to verstage main function
+	blx	r2
+
+// This point should not be reached. The Main() function should return
+// to main BL using Svc_Exit().
+//
+ShouldNotBeReached:
+	mov	r0, #BL_ERR_GENERIC     // Returned from Main
+	svc	#0x0                    // SVC_EXIT
+
+ENDPROC(_psp_vs_start)
+.end
diff --git a/src/vendorcode/amd/fsp/sabrina/dmi_info.h b/src/vendorcode/amd/fsp/sabrina/dmi_info.h
new file mode 100644
index 0000000000..d2c26fad4c
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/dmi_info.h
@@ -0,0 +1,239 @@
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+/**
+ * This code was copied from src/vendorcode/amd/pi/00670F00/AGESA.h
+ */
+
+#define AMD_FSP_DMI_HOB_GUID  {0x4118FC0E, 0x353D, 0x4726, { 0x97, 0xC0, 0x53, 0xCD, 0x92, 0xB6, 0x49, 0x25}}
+
+// Our ACPI HOB max payload, accounting for the size of the HOB header as well as the information structure
+#define HOB_MAX_SIZE                0xFFF8
+#define HOB_GUID_EXTENSION_SIZE     (HOB_MAX_SIZE - sizeof (EFI_HOB_GUID_TYPE))
+
+#define MAX_SOCKETS_SUPPORTED     2   ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET   8   ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL     4   ///< Max DIMMs on a memory channel (independent of platform)
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+  OtherLocation = 0x01,                                 ///< Assign 01 to Other
+  UnknownLocation,                                      ///< Assign 02 to Unknown
+  SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
+  IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
+  EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
+  PciAddonCard,                                         ///< Assign 06 to PCI add-on card
+  McaAddonCard,                                         ///< Assign 07 to MCA add-on card
+  PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
+  ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
+  NuBus,                                                ///< Assign 0A to NuBus
+  Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
+  Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
+  Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
+  Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+  OtherUse = 0x01,                                      ///< Assign 01 to Other
+  UnknownUse,                                           ///< Assign 02 to Unknown
+  SystemMemory,                                         ///< Assign 03 to system memory
+  VideoMemory,                                          ///< Assign 04 to video memory
+  FlashMemory,                                          ///< Assign 05 to flash memory
+  NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
+  CacheMemory                                           ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+  Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
+  Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
+  Dmi16NoneErrCorrection,                               ///< Assign 03 to None
+  Dmi16Parity,                                          ///< Assign 04 to parity
+  Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
+  Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
+  Dmi16Crc                                              ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+  OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
+                                                        ///< whether on the system board or an add-in board.
+  OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
+                                                        ///< is used.
+  OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
+                                                        ///< detection method supported by this memory array.
+  OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
+                                                        ///< for memory devices in this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+  OtherFormFactor = 0x01,                               ///< Assign 01 to Other
+  UnknowFormFactor,                                     ///< Assign 02 to Unknown
+  SimmFormFactor,                                       ///< Assign 03 to SIMM
+  SipFormFactor,                                        ///< Assign 04 to SIP
+  ChipFormFactor,                                       ///< Assign 05 to Chip
+  DipFormFactor,                                        ///< Assign 06 to DIP
+  ZipFormFactor,                                        ///< Assign 07 to ZIP
+  ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
+  DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
+  TsopFormFactor,                                       ///< Assign 10 to TSOP
+  RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
+  RimmFormFactor,                                       ///< Assign 12 to RIMM
+  SodimmFormFactor,                                     ///< Assign 13 to SODIMM
+  SrimmFormFactor,                                      ///< Assign 14 to SRIMM
+  FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+  OtherMemType = 0x01,                                  ///< Assign 01 to Other
+  UnknownMemType,                                       ///< Assign 02 to Unknown
+  DramMemType,                                          ///< Assign 03 to DRAM
+  EdramMemType,                                         ///< Assign 04 to EDRAM
+  VramMemType,                                          ///< Assign 05 to VRAM
+  SramMemType,                                          ///< Assign 06 to SRAM
+  RamMemType,                                           ///< Assign 07 to RAM
+  RomMemType,                                           ///< Assign 08 to ROM
+  FlashMemType,                                         ///< Assign 09 to Flash
+  EepromMemType,                                        ///< Assign 10 to EEPROM
+  FepromMemType,                                        ///< Assign 11 to FEPROM
+  EpromMemType,                                         ///< Assign 12 to EPROM
+  CdramMemType,                                         ///< Assign 13 to CDRAM
+  ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
+  SdramMemType,                                         ///< Assign 15 to SDRAM
+  SgramMemType,                                         ///< Assign 16 to SGRAM
+  RdramMemType,                                         ///< Assign 17 to RDRAM
+  DdrMemType,                                           ///< Assign 18 to DDR
+  Ddr2MemType,                                          ///< Assign 19 to DDR2
+  Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
+  Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
+  Fbd2MemType,                                          ///< Assign 25 to FBD2
+  Ddr4MemType,                                          ///< Assign 26 to DDR4
+  LpDdrMemType,                                         ///< Assign 27 to LPDDR
+  LpDdr2MemType,                                        ///< Assign 28 to LPDDR2
+  LpDdr3MemType,                                        ///< Assign 29 to LPDDR3
+  LpDdr4MemType,                                        ///< Assign 30 to LPDDR4
+  LpDdr5MemType,                                        ///< Assign 31 to LPDDR5
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+  OUT UINT16                    Reserved1:1;            ///< Reserved
+  OUT UINT16                    Other:1;                ///< Other
+  OUT UINT16                    Unknown:1;              ///< Unknown
+  OUT UINT16                    FastPaged:1;            ///< Fast-Paged
+  OUT UINT16                    StaticColumn:1;         ///< Static column
+  OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
+  OUT UINT16                    Rambus:1;               ///< RAMBUS
+  OUT UINT16                    Synchronous:1;          ///< Synchronous
+  OUT UINT16                    Cmos:1;                 ///< CMOS
+  OUT UINT16                    Edo:1;                  ///< EDO
+  OUT UINT16                    WindowDram:1;           ///< Window DRAM
+  OUT UINT16                    CacheDram:1;            ///< Cache Dram
+  OUT UINT16                    NonVolatile:1;          ///< Non-volatile
+  OUT UINT16                    Registered:1;           ///< Registered (Buffered)
+  OUT UINT16                    Unbuffered:1;           ///< Unbuffered (Unregistered)
+  OUT UINT16                    LRDIMM:1;               ///< LRDIMM
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 offset 28h - Memory Technology
+typedef enum {
+  OtherType = 0x01,                                     ///< Assign 01 to Other
+  UnknownType = 0x02,                                   ///< Assign 02 to Unknown
+  DramType = 0x03,                                      ///< Assign 03 to DRAM
+  NvDimmNType = 0x04,                                   ///< Assign 04 to NVDIMM-N
+  NvDimmFType = 0x05,                                   ///< Assign 05 to NVDIMM-F
+  NvDimmPType = 0x06,                                   ///< Assign 06 to NVDIMM-P
+  IntelPersistentMemoryType = 0x07,                     ///< Assign 07 to Intel persistent memory
+} DMI_T17_MEMORY_TECHNOLOGY;
+
+/// DMI Type 17 offset 29h - Memory Operating Mode Capability
+typedef struct {
+  OUT UINT16                    Reserved1:1;            ///< Reserved, set to 0
+  OUT UINT16                    Other:1;                ///< Other
+  OUT UINT16                    Unknown:1;              ///< Unknown
+  OUT UINT16                    VolatileMemory:1;       ///< Volatile memory
+  OUT UINT16                    ByteAccessiblePersistentMemory:1;    ///< Byte-accessible persistent memory
+  OUT UINT16                    BlockAccessiblePersistentMemory:1;   ///< Block-accessible persistent memory
+  OUT UINT16                    Reserved2:10;           ///< Reserved, set to 0
+} DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY;
+
+typedef union {
+  DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY  AsBitmap;
+  UINT16                                    AsUint16;
+} DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+  OUT UINT16                    Handle;                 ///< The temporary handle, or instance number, associated with the structure
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
+                                                        ///< Memory Devices that must be populated with all devices of
+                                                        ///< the same type and size, and the set to which this device belongs.
+  OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT CHAR8                     BankLocator[13];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
+  OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
+  OUT CHAR8                     PartNumber[21];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+  OUT UINT16                    MinimumVoltage;         ///< Minimum operating voltage for this device, in millivolts
+  OUT UINT16                    MaximumVoltage;         ///< Maximum operating voltage for this device, in millivolts
+  OUT UINT16                    ConfiguredVoltage;      ///< Configured voltage for this device, in millivolts
+  // SMBIOS 3.2
+  OUT UINT8                     MemoryTechnology;       ///< Memory technology type for this memory device
+  OUT DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR   MemoryOperatingModeCapability; ///< The operating modes supported by this memory device
+  OUT CHAR8                     FirmwareVersion[10];    ///< String number for the firmware version of this memory device
+  OUT UINT16                    ModuleManufacturerId;   ///< The two-byte module manufacturer ID found in the SPD of this memory device; LSB first.
+  OUT UINT16                    ModuleProductId;        ///< The two-byte module product ID found in the SPD of this memory device; LSB first
+  OUT UINT16                    MemorySubsystemControllerManufacturerId; //< The two-byte memory subsystem controller manufacturer ID found in the SPD of this memory device; LSB first
+  OUT UINT16                    MemorySubsystemControllerProductId; //< The two-byte memory subsystem controller product ID found in the SPD of this memory device; LSB first
+  OUT UINT64                    NonvolatileSize;        ///< Size of the Non-volatile portion of the memory device in Bytes, if any.
+  OUT UINT64                    VolatileSize;           ///< Size of the Volatile portion of the memory device in Bytes, if any.
+  OUT UINT64                    CacheSize;              ///< Size of the Cache portion of the memory device in Bytes, if any.
+  OUT UINT64                    LogicalSize;            ///< Size of the Logical memory device in Bytes.
+  // SMBIOS 3.3
+  OUT UINT32                    ExtendedSpeed;          ///< Extended Speed
+  OUT UINT32                    ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed
+} __packed TYPE17_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+  OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
+  OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+} DMI_INFO;
diff --git a/src/vendorcode/amd/fsp/sabrina/fsp_h_c99.h b/src/vendorcode/amd/fsp/sabrina/fsp_h_c99.h
new file mode 100644
index 0000000000..1a295f591a
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/fsp_h_c99.h
@@ -0,0 +1,58 @@
+/** @file
+ *
+ * C99 common FSP definitions from
+ * Intel Firmware Support Package External Architecture Specification v2.0
+ *
+ * These definitions come in a format that is usable outside an EFI environment.
+ **/
+#ifndef FSP_H_C99_H
+#define FSP_H_C99_H
+
+#include <stdint.h>
+
+enum {
+	FSP_STATUS_RESET_REQUIRED_COLD		= 0x40000001,
+	FSP_STATUS_RESET_REQUIRED_WARM		= 0x40000002,
+	FSP_STATUS_RESET_REQUIRED_3		= 0x40000003,
+	FSP_STATUS_RESET_REQUIRED_4		= 0x40000004,
+	FSP_STATUS_RESET_REQUIRED_5		= 0x40000005,
+	FSP_STATUS_RESET_REQUIRED_6		= 0x40000006,
+	FSP_STATUS_RESET_REQUIRED_7		= 0x40000007,
+	FSP_STATUS_RESET_REQUIRED_8		= 0x40000008,
+};
+
+typedef enum {
+	EnumInitPhaseAfterPciEnumeration	= 0x20,
+	EnumInitPhaseReadyToBoot		= 0x40,
+	EnumInitPhaseEndOfFirmware		= 0xF0
+} FSP_INIT_PHASE;
+
+typedef struct __packed {
+	uint64_t	Signature;
+	uint8_t		Revision;
+	uint8_t		Reserved[23];
+} FSP_UPD_HEADER;
+
+_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
+
+
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
+typedef struct __packed {
+	uint8_t		Revision;
+	uint8_t		Reserved[3];
+	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
+	uint32_t	NvsBufferPtr;
+	/* Note: This ought to be void*, but that won't allow calling this binary on x86_64. */
+	uint32_t	StackBase;
+	uint32_t	StackSize;
+	uint32_t	BootLoaderTolumSize;
+	uint32_t	BootMode;
+	uint8_t		Reserved1[8];
+} FSPM_ARCH_UPD;
+
+_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
+
+#endif /* FSP_H_C99_H */
diff --git a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_errorcodes_public.h b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_errorcodes_public.h
new file mode 100644
index 0000000000..4fa9a3371f
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_errorcodes_public.h
@@ -0,0 +1,37 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2020, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *******************************************************************************/
+
+#ifndef BL_ERRORCODES_PUBLIC_H
+#define BL_ERRORCODES_PUBLIC_H
+
+/* Bootloader Return Codes, Error only (0x00 through 0x9F) */
+#define BL_OK					0x00	// General - Success
+#define BL_ERR_GENERIC				0x01	// Generic Error Code
+
+#endif /* BL_ERRORCODES_PUBLIC_H */
diff --git a/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h
new file mode 100644
index 0000000000..06e9defea7
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/include/bl_uapp/bl_syscall_public.h
@@ -0,0 +1,319 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2020, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _BL_SYSCALL_PUBLIC_H_
+#define _BL_SYSCALL_PUBLIC_H_
+
+#include <stdint.h>
+
+#define SVC_EXIT                            0x00
+#define SVC_ENTER                           0x02
+#define SVC_DEBUG_PRINT                     0x06
+#define SVC_MODEXP                          0x0C
+#define SVC_DEBUG_PRINT_EX                  0x1A
+#define SVC_GET_BOOT_MODE                   0x1C
+#define SVC_DELAY_IN_MICRO_SECONDS          0x2F
+#define SVC_GET_SPI_INFO                    0x60
+#define SVC_MAP_SPIROM_DEVICE               0x61
+#define SVC_UNMAP_SPIROM_DEVICE             0x62
+#define SVC_MAP_FCH_IO_DEVICE               0x63
+#define SVC_UNMAP_FCH_IO_DEVICE             0x64
+#define SVC_UPDATE_PSP_BIOS_DIR             0x65
+#define SVC_COPY_DATA_FROM_UAPP             0x66
+#define SVC_RESET_SYSTEM                    0x67
+#define SVC_READ_TIMER_VAL                  0x68
+#define SVC_SHA                             0x69
+#define SVC_CCP_DMA                         0x6A
+
+struct mod_exp_params {
+	char		*pExponent;	// Exponent address
+	unsigned int	ExpSize;	// Exponent size in bytes
+	char		*pModulus;	// Modulus address
+	unsigned int	ModulusSize;	// Modulus size in bytes
+	char		*pMessage;	// Message address, same size as ModulusSize
+	char		*pOutput;	// Output address; Must be big enough to hold the
+					// data of ModulusSize
+};
+
+enum psp_boot_mode {
+	PSP_BOOT_MODE_S0 = 0x0,
+	PSP_BOOT_MODE_S0i3_RESUME = 0x1,
+	PSP_BOOT_MODE_S3_RESUME = 0x2,
+	PSP_BOOT_MODE_S4 = 0x3,
+	PSP_BOOT_MODE_S5_COLD = 0x4,
+	PSP_BOOT_MODE_S5_WARM = 0x5,
+};
+
+enum reset_type
+{
+	RESET_TYPE_COLD    = 0,
+	RESET_TYPE_WARM    = 1,
+	RESET_TYPE_MAX     = 2,
+};
+
+enum fch_io_device {
+	FCH_IO_DEVICE_SPI,
+	FCH_IO_DEVICE_I2C,
+	FCH_IO_DEVICE_GPIO,
+	FCH_IO_DEVICE_ESPI,
+	FCH_IO_DEVICE_IOMUX,
+	FCH_IO_DEVICE_MISC,
+	FCH_IO_DEVICE_AOAC,
+	FCH_IO_DEVICE_IOPORT,
+
+	FCH_IO_DEVICE_END,
+};
+
+enum fch_i2c_controller_id {
+	FCH_I2C_CONTROLLER_ID_0 = 0,
+	FCH_I2C_CONTROLLER_ID_1 = 1,
+	FCH_I2C_CONTROLLER_ID_2 = 2,
+	FCH_I2C_CONTROLLER_ID_3 = 3,
+	FCH_I2C_CONTROLLER_ID_MAX,
+};
+
+struct spirom_info {
+	void *SpiBiosSysHubBase;
+	void *SpiBiosSmnBase;
+	uint32_t SpiBiosSize;
+};
+
+enum psp_timer_type {
+	PSP_TIMER_TYPE_CHRONO     = 0,
+	PSP_TIMER_TYPE_SECURE_RTC = 1,
+	PSP_TIMER_TYPE_MAX        = 2,
+};
+
+/* SHA types same as ccp SHA type in crypto.h */
+enum sha_type {
+	SHA_TYPE_256,
+	SHA_TYPE_384
+};
+
+/* All SHA operation supported */
+enum sha_operation_mode {
+	SHA_GENERIC
+};
+
+/* SHA Supported Data Structures */
+struct sha_generic_data {
+	enum sha_type	SHAType;
+	uint8_t		*Data;
+	uint32_t	DataLen;
+	uint32_t	DataMemType;
+	uint8_t		*Digest;
+	uint32_t	DigestLen;
+	uint8_t		*IntermediateDigest;
+	uint32_t	IntermediateMsgLen;
+	uint32_t	Init;
+	uint32_t	Eom;
+};
+
+/*
+ * Exit to the main Boot Loader. This does not return back to user application.
+ *
+ * Parameters:
+ *     status  -   either Ok or error code defined by AGESA
+ */
+void svc_exit(uint32_t status);
+
+/* Print debug message into serial console.
+ *
+ * Parameters:
+ *     string     -   null-terminated string
+ */
+void svc_debug_print(const char *string);
+
+/* Print 4 DWORD values in hex to serial console
+ *
+ * Parameters:
+ *     dword0...dword3 - 32-bit DWORD to print
+ */
+void svc_debug_print_ex(uint32_t dword0,
+		uint32_t dword1, uint32_t dword2, uint32_t dword3);
+
+/* Description     - Returns the current boot mode from the enum psp_boot_mode found in
+ *                   bl_public.h.
+ *
+ * Inputs          - boot_mode - Output parameter passed in R0
+ *
+ * Outputs         - The boot mode in boot_mode.
+ *                   See Return Values.
+ *
+ * Return Values   - BL_OK
+ *                   BL_ERR_NULL_PTR
+ *                   Other BL_ERRORs lofted up from called functions
+ */
+uint32_t svc_get_boot_mode(uint32_t *boot_mode);
+
+/* Add delay in micro seconds
+ *
+ * Parameters:
+ *     delay       - required delay value in microseconds
+ *
+ * Return value: NONE
+ */
+void svc_delay_in_usec(uint32_t delay);
+
+/* Get the SPI-ROM information
+ *
+ * Parameters:
+ *     spi_rom_iInfo  - SPI-ROM information
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info);
+
+/* Map the FCH IO device register space (SPI/I2C/GPIO/eSPI/etc...)
+ *
+ * Parameters:
+ *     io_device         - ID for respective FCH IO controller register space to be mapped
+ *     arg1              - Based on IODevice ID, interpretation of this argument changes.
+ *     arg2              - Based on IODevice ID, interpretation of this argument changes.
+ *     io_device_axi_addr    - AXI address for respective FCH IO device register space
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_map_fch_dev(enum fch_io_device io_device,
+		uint32_t arg1, uint32_t arg2, void **io_device_axi_addr);
+
+/* Unmap the FCH IO device register space mapped earlier using Svc_MapFchIODevice()
+ *
+ * Parameters:
+ *     io_device        - ID for respective FCH IO controller register space to be unmapped
+ *     io_device_addr   - AXI address for respective FCH IO device register space
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_unmap_fch_dev(enum fch_io_device io_device,
+		void *io_device_axi_addr);
+
+/* Map the SPIROM FLASH device address space
+ *
+ * Parameters:
+ *     SpiRomAddr     - Address in SPIROM tobe mapped (SMN based)
+ *     size           - Size to be mapped
+ *     pSpiRomAddrAxi - Mapped address in AXI space
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_map_spi_rom(void *spi_rom_addr,
+		uint32_t size, void **spi_rom_axi_addr);
+
+/* Unmap the SPIROM FLASH device address space mapped earlier using Svc_MapSpiRomDevice()
+ *
+ * Parameters:
+ *     pSpiRomAddrAxi - Address in AXI address space previously mapped
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_unmap_spi_rom(void *spi_rom_addr);
+
+/* Updates the offset at which PSP or BIOS Directory can be found in the
+ * SPI flash
+ *
+ * Parameters:
+ *     psp_dir_offset - [in/out] Offset at which PSP Directory can be
+ *                      found in the SPI Flash. Same pointer is used
+ *                      to return the offset in case of GET operation
+ *     bios_dir_offset - [in/out] Offset at which BIOS Directory can be
+ *                       found in the SPI Flash. Same pointer is used
+ *                       to return the offset in case of GET operation
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset,
+		uint32_t *bios_dir_offset);
+
+/* Copies the data that is shared by verstage to the PSP BL owned memory
+ *
+ * Parameters:
+ *     address - Address in UAPP controlled/owned memory
+ *     size    - Total size of memory to copy (max 16Kbytes)
+ */
+uint32_t svc_save_uapp_data(void *address, uint32_t size);
+
+/*
+ *    Read timer raw (currently CHRONO and RTC) value
+ *
+ *    Parameters:
+ *                type            - [in] Type of timer UAPP would like to read from
+ *                                  (currently CHRONO and RTC)
+ *                counter_value   - [out] return the raw counter value read from
+ *                                  RTC or CHRONO_LO/HI counter register
+ -----------------------------------------------------------------------------*/
+uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value);
+
+/*
+ *    Reset the system
+ *
+ *   Parameters:
+ *      reset_type -   Cold or Warm reset
+ */
+uint32_t svc_reset_system(enum reset_type reset_type);
+
+/*
+ *    Write postcode to Port-80
+ *
+ *    Parameters:
+ *                postcode -   Postcode value to be written on port-80h
+ */
+uint32_t svc_write_postcode(uint32_t postcode);
+
+/*
+ * Generic SHA call for SHA, SHA_OTP, SHA_HMAC
+ */
+uint32_t svc_crypto_sha(struct sha_generic_data *sha_op, enum sha_operation_mode sha_mode);
+
+/*
+ * Calculate ModEx
+ *
+ * Parameters:
+ *       mod_exp_param - ModExp parameters
+ *
+ *   Return value: BL_OK or error code
+ */
+uint32_t svc_modexp(struct mod_exp_params *mod_exp_param);
+
+/*
+ * Copies the data from source to destination using ccp
+ *
+ * Parameters:
+ *   Source Address - SPI ROM offset
+ *   Destination Address - Address in Verstage memory
+ *   Size    - Total size to copy
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_ccp_dma(uint32_t spi_rom_offset, void *dest, uint32_t size);
+
+/* C entry point for the Bootloader Userspace Application */
+void Main(void);
+
+#endif /* _BL_SYSCALL__PUBLIC_H_ */
diff --git a/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h b/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h
new file mode 100644
index 0000000000..ada9bbd209
--- /dev/null
+++ b/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * These definitions are used to describe PCIe bifurcation and display physical
+ * connector types connected to the SOC.
+ */
+
+#ifndef PI_CEZANNE_PLATFORM_DESCRIPTORS_H
+#define PI_CEZANNE_PLATFORM_DESCRIPTORS_H
+
+#define NUM_DXIO_PHY_PARAMS	6
+#define NUM_DXIO_PORT_PARAMS	6
+
+/* Engine descriptor type */
+enum dxio_engine_type {
+	UNUSED_ENGINE	= 0x00,	// Unused descriptor
+	PCIE_ENGINE	= 0x01,	// PCIe port
+	USB_ENGINE	= 0x02,	// USB port
+	SATA_ENGINE	= 0x03,	// SATA
+	DP_ENGINE	= 0x08,	// Digital Display
+	ETHERNET_ENGINE	= 0x10,	// Ethernet (GBe, XGBe)
+	MAX_ENGINE		// Max engine type for boundary check.
+};
+
+/* PCIe link capability/speed */
+enum dxio_link_speed_cap {
+	GEN_MAX = 0,		// Maximum supported
+	GEN1,
+	GEN2,
+	GEN3,
+	GEN_INVALID		// Max Gen for boundary check
+};
+
+/* Upstream Auto Speed Change Allowed */
+enum dxio_upstream_auto_speed_change {
+	SPDC_DEFAULT = 0,      // Enabled for Gen2 and Gen3
+	SPDC_DISABLED,
+	SPDC_ENABLED,
+	SPDC_INVALID
+};
+
+/* SATA ChannelType initialization */
+enum dxio_sata_channel_type {
+	SATA_CHANNEL_OTHER = 0,	// Default Channel Type
+	SATA_CHANNEL_SHORT,	// Short Trace Channel Type
+	SATA_CHANNEL_LONG	// Long Trace Channel Type
+};
+
+/* CLKREQ for PCIe type descriptors */
+enum cpm_clk_req {
+	CLK_DISABLE = 0x00,
+	CLK_REQ0,
+	CLK_REQ1,
+	CLK_REQ2,
+	CLK_REQ3,
+	CLK_REQ4_GFX,
+	CLK_REQ5,
+	CLK_REQ6,
+	CLK_ENABLE = 0xff,
+};
+
+/* PCIe link ASPM initialization */
+enum dxio_aspm_type {
+	ASPM_DISABLED = 0,	// Disabled
+	ASPM_L0s,		// PCIe L0s link state
+	ASPM_L1,		// PCIe L1 link state
+	ASPM_L0sL1,		// PCIe L0s & L1 link state
+	ASPM_MAX		// Not valid value, used to verify input
+};
+
+enum dxio_port_param_type {
+	PP_DEVICE = 1,
+	PP_FUNCTION,
+	PP_PORT_PRESENT,
+	PP_LINK_SPEED_CAP,
+	PP_LINK_ASPM,
+	PP_HOTPLUG_TYPE,
+	PP_CLKREQ,
+	PP_ASPM_L1_1,
+	PP_ASPM_L1_2,
+	PP_COMPLIANCE,
+	PP_SAFE_MODE,
+	PP_CHIPSET_LINK,
+	PP_CLOCK_PM,
+	PP_CHANNELTYPE,
+	PP_TURN_OFF_UNUSED_LANES,
+	PP_APIC_GROUPMAP,
+	PP_APIC_SWIZZLE,
+	PP_APIC_BRIDGEINT,
+	PP_MASTER_PLL,
+	PP_SLOT_NUM,
+	PP_PHY_PARAM,
+	PP_ESM,
+	PP_CCIX,
+	PP_GEN3_DS_TX_PRESET,
+	PP_GEN3_DS_RX_PRESET_HINT,
+	PP_GEN3_US_TX_PRESET,
+	PP_GEN3_US_RX_PRESET_HINT,
+	PP_GEN4_DS_TX_PRESET,
+	PP_GEN4_US_TX_PRESET,
+	PP_GEN3_FIXED_PRESET,
+	PP_GEN4_FIXED_PRESET,
+	PP_PSPP_DC,
+	PP_PSPP_AC,
+	PP_GEN2_DEEMPHASIS,
+	PP_INVERT_POLARITY,
+	PP_TARGET_LINK_SPEED,
+	PP_GEN4_DLF_CAP_DISABLE,
+	PP_GEN4_DLF_EXCHG_DISABLE
+};
+
+/* DDI Aux channel */
+enum ddi_aux_type {
+	DDI_AUX1 = 0,
+	DDI_AUX2,
+	DDI_AUX3,
+	DDI_AUX4,
+	DDI_AUX5,
+	DDI_AUX6,
+	DDI_AUX_MAX		// Not valid value, used to verify input
+};
+
+/* DDI Hdp Index */
+enum ddi_hdp_type {
+	DDI_HDP1 = 0,
+	DDI_HDP2,
+	DDI_HDP3,
+	DDI_HDP4,
+	DDI_HDP5,
+	DDI_HDP6,
+	DDI_HDP_MAX		// Not valid value, used to verify input
+};
+
+/* DDI display connector type */
+enum ddi_connector_type {
+	DDI_DP = 0,		// DP
+	DDI_EDP,		// eDP
+	DDI_SINGLE_LINK_DVI,	// Single Link DVI-D
+	DDI_DUAL_LINK_DVI,	// Dual Link DVI-D
+	DDI_HDMI,		// HDMI
+	DDI_DP_TO_VGA,		// DP-to-VGA
+	DDI_DP_TO_LVDS,		// DP-to-LVDS
+	DDI_NUTMEG_DP_TO_VGA,	// Hudson-2 NutMeg DP-to-VGA
+	DDI_SINGLE_LINK_DVI_I,	// Single Link DVI-I
+	DDI_CRT,		// CRT (VGA)
+	DDI_LVDS,		// LVDS
+	DDI_EDP_TO_LVDS,	// eDP-to-LVDS translator chip without AMD SW init
+	DDI_EDP_TO_LVDS_SW,	// eDP-to-LVDS translator which requires AMD SW init
+	DDI_AUTO_DETECT,	// VBIOS auto detect connector type
+	DDI_UNUSED_TYPE,	// UnusedType
+	DDI_MAX_CONNECTOR_TYPE	// Not valid value, used to verify input
+};
+
+/* Cezanne DDI Descriptor: used for configuring display outputs */
+typedef struct __packed {
+	uint8_t		connector_type;	// see ddi_connector_type
+	uint8_t		aux_index;	// see ddi_aux_type
+	uint8_t		hdp_index;	// see ddi_hdp_type
+	uint8_t		reserved;
+} fsp_ddi_descriptor;
+
+/*
+ * Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines,
+ * configure bifurcation and other settings. Beware that the lane numbers in
+ * here are the logical and not the physical lane numbers!
+ *
+ * Cezanne DXIO logical lane to physical PCIe lane mapping:
+ *
+ * logical |   FT6      |   AM4
+ * --------|------------|----------------------
+ * [00:03] | GPP[00:03] | GPP[00:03]
+ * [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03]
+ * [08:11] | GPP[08:11] | GFX[15:12]
+ * [12:15] |        n/a | GFX[11:08]
+ * [16:23] | GFX[00:07] | GFX[07:0]
+ *
+ * Different ports mustn't overlap or be assigned to the same lane(s). Within
+ * ports with the same width the one with a higher start logical lane number
+ * needs to be assigned to a higher PCIe root port number; ports of the same
+ * size don't have to be assigned to consecutive PCIe root ports though.
+ *
+ * Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6
+ * platform additionally supports mapping lanes 8 and 9 to a SATA controller.
+ * On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet
+ * controllers.
+ */
+typedef struct __packed {
+	uint8_t		engine_type;			// See dxio_engine_type
+	uint8_t		start_logical_lane;		// Start lane of the pci device
+	uint8_t		end_logical_lane;		// End lane of the pci device
+	uint8_t		gpio_group_id;			// GPIO number used as reset
+	uint32_t	port_present		:1;	// Should be TRUE if train link
+	uint32_t	reserved_3		:7;
+	uint32_t	device_number		:5;	// Desired root port device number
+	uint32_t	function_number		:3;	// Desired root port function number
+	uint32_t	link_speed_capability	:2;	// See dxio_link_speed_cap
+	uint32_t	auto_spd_change		:2;	// See dxio_upstream_auto_speed_change
+	uint32_t	eq_preset		:4;	// Gen3 equalization preset
+	uint32_t	link_aspm		:2;	// See dxio_aspm_type
+	uint32_t	link_aspm_L1_1		:1;	// En/Dis root port capabilities for L1.1
+	uint32_t	link_aspm_L1_2		:1;	// En/Dis root port capabilities for L1.2
+	uint32_t	clk_req			:4;	// See cpm_clk_req
+	uint8_t		link_hotplug;			// Currently unused by FSP
+	uint8_t		slot_power_limit;		// Currently unused by FSP
+	uint32_t	slot_power_limit_scale	:2;	// Currently unused by FSP
+	uint32_t	reserved_4		:6;
+	uint32_t	link_compliance_mode	:1;	// Currently unused by FSP
+	uint32_t	link_safe_mode		:1;	// Currently unused by FSP
+	uint32_t	sb_link			:1;	// Currently unused by FSP
+	uint32_t	clk_pm_support		:1;	// Currently unused by FSP
+	uint32_t	channel_type		:3;	// See dxio_sata_channel_type
+	uint32_t	turn_off_unused_lanes	:1;	// Power down lanes if device not present
+	uint8_t		reserved[4];
+	uint8_t		phy_params[NUM_DXIO_PHY_PARAMS*2];
+	uint16_t	port_params[NUM_DXIO_PORT_PARAMS*2];	// key-value parameters. see dxio_port_param_type
+} fsp_dxio_descriptor;
+
+#endif /* PI_CEZANNE_PLATFORM_DESCRIPTORS_H */