vendorcode/mt8192: change to short log macro names

Originally, log macro names are too long, and they use
double parentheses style: ((...)), which causes compile
or runtime error easily.
Now, change them to single parenthesis mode (...), and
use shorter name.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2959dc1ba0dd40a8fb954406072f31cf14c26667
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

18 files changed, 1283 insertions, 1281 deletions

diff --git a/src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c b/src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c
index d8fd41f451..a03454640d 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/ANA_init_config.c
@@ -32,10 +32,10 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
 	PCW    = (PLL_FREQ/XTAL_FREQ) << (8+1-FBKSEL-PREDIV-POSDIV);
 
 
-	mcSHOW_DBG_MSG((">>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL\n"));
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("data_rate = %d,PCW = 0X%x\n",data_rate,PCW));
-	mcSHOW_DBG_MSG(("=================================== \n"));
+	msg(">>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL\n");
+	msg("=================================== \n");
+	msg("data_rate = %d,PCW = 0X%x\n",data_rate,PCW);
+	msg("=================================== \n");
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL1), P_Fld(0, PHYPLL1_RG_RPHYPLL_TST_EN) | P_Fld(0, PHYPLL1_RG_RPHYPLL_TSTOP_EN));
 	// @Darren, Mp settings sync @WL
@@ -72,7 +72,7 @@ static void ANA_PLL_shuffle_Config(DRAMC_CTX_T *p,U32 PLL_FREQ,U16 data_rate)
 																  | P_Fld( DIV16_CK_SEL 		 , SHU_CLRPLL3_RG_RCLRPLL_DIV_CK_SEL	   )); //@Darren, DDR250 = 4G/div16, confirm with WL Lee
 	}
 //	  vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_PLL2)		, P_Fld(1			, SHU_PLL2_RG_RPHYPLL_ADA_MCK8X_EN_SHU	  ));
-	mcSHOW_DBG_MSG(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL\n"));
+	msg("<<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL\n");
 }
 
 
@@ -83,13 +83,13 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
 	U8 ARDLL_SERMODE_B=0;
 	U8 ARDLL_SERMODE_C=0;
 
-	mcSHOW_DBG_MSG((">>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n"));
+	msg(">>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n");
 	switch (tr->DQ_P2S_RATIO)
 	{
 		case 4 : { TX_ARDQ_SERMODE = 1; break; }
 		case 8 : { TX_ARDQ_SERMODE = 2; break; }
 		case 16: { TX_ARDQ_SERMODE = 3; break; }
-		default: mcSHOW_DBG_MSG(("ERROR: tr->DQ_P2S_RATIO= %2d, Not support!!",tr->DQ_P2S_RATIO));
+		default: msg("ERROR: tr->DQ_P2S_RATIO= %2d, Not support!!",tr->DQ_P2S_RATIO);
 	}
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ14), P_Fld(  TX_ARDQ_SERMODE	  , SHU_B0_DQ14_RG_TX_ARDQ_SER_MODE_B0		  ));
@@ -107,7 +107,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
 		case 2 : { TX_ARCA_SERMODE = (0 + tr->CA_FULL_RATE); break; }
 		case 4 : { TX_ARCA_SERMODE = (1 + tr->CA_FULL_RATE); break; }
 		case 8:  { TX_ARCA_SERMODE = (2 + tr->CA_FULL_RATE); break; }
-		default: mcSHOW_DBG_MSG(("ERROR: tr->CA_P2S_RATIO= %2d, Not support!!",tr->CA_P2S_RATIO));
+		default: msg("ERROR: tr->CA_P2S_RATIO= %2d, Not support!!",tr->CA_P2S_RATIO);
 	}
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD14), P_Fld(TX_ARCA_SERMODE, SHU_CA_CMD14_RG_TX_ARCA_SER_MODE_CA));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD6),	P_Fld(TX_ARCA_SERMODE, SHU_CA_CMD6_RG_RX_ARCMD_RANK_SEL_SER_MODE));
@@ -117,7 +117,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
 		case 2 : { ARDLL_SERMODE_B = 1; break; }
 		case 4 : { ARDLL_SERMODE_B = 2; break; }
 		case 8:  { ARDLL_SERMODE_B = 3; break; }
-		default: mcSHOW_DBG_MSG(("WARN: tr->DQ_AAMCK_DIV= %2d, Because of DQ_SEMI_OPEN, It's don't care.",tr->DQ_AAMCK_DIV));
+		default: msg("WARN: tr->DQ_AAMCK_DIV= %2d, Because of DQ_SEMI_OPEN, It's don't care.",tr->DQ_AAMCK_DIV);
 	}
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1), P_Fld(ARDLL_SERMODE_B			 , SHU_B0_DLL1_RG_ARDLL_SER_MODE_B0));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1), P_Fld(ARDLL_SERMODE_B			 , SHU_B1_DLL1_RG_ARDLL_SER_MODE_B1));
@@ -127,7 +127,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
 		case 2 : { ARDLL_SERMODE_C = 1; break; }
 		case 4 : { ARDLL_SERMODE_C = 2; break; }
 		case 8:  { ARDLL_SERMODE_C = 3; break; }
-		default: mcSHOW_DBG_MSG(("ERROR: tr->CA_ADMCK_DIV= %2d, Not support!!",tr->CA_ADMCK_DIV));
+		default: msg("ERROR: tr->CA_ADMCK_DIV= %2d, Not support!!",tr->CA_ADMCK_DIV);
 	}
 	DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
 	vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL1),	P_Fld(ARDLL_SERMODE_C			, SHU_CA_DLL1_RG_ARDLL_SER_MODE_CA));
@@ -205,7 +205,7 @@ static void ANA_CLK_DIV_config_setting(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_to
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)		 , P_Fld( tr->DQ_TRACK_CA_EN, SHU_B0_DLL1_RG_ARDLL_TRACKING_CA_EN_B0 ));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)		 , P_Fld( tr->DQ_TRACK_CA_EN, SHU_B1_DLL1_RG_ARDLL_TRACKING_CA_EN_B1 ));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_DLL_ARPI2)	 , P_Fld( 1 				, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN	 ));
-  mcSHOW_DBG_MSG(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n"));
+  msg("<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration\n");
 }
 
 //==========================
@@ -319,10 +319,10 @@ static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg)
 	if(p->frequency<=1600)
 	{
 		u1Gain = 2;
-		mcSHOW_DBG_MSG((">>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = %d\n",u1Gain));
+		msg(">>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = %d\n",u1Gain);
 	}
 
-	mcSHOW_DBG_MSG((">>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL\n"));
+	msg(">>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL\n");
 	if(a_cfg->DLL_ASYNC_EN == 1)
 	{
 	  DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
@@ -439,7 +439,7 @@ static void ANA_DLL_shuffle_Config(DRAMC_CTX_T *p, ANA_top_config_T *a_cfg)
 																	 | P_Fld(  1					   , SHU_B1_DLL1_RG_ARDLL_UDIV_EN_B1	  ) \
 																	 | P_Fld(  1					   , SHU_B1_DLL1_RG_ARDLL_PS_EN_B1		  ) \
 																	 | P_Fld(  0					   , SHU_B1_DLL1_RG_ARDLL_PD_CK_SEL_B1	  ));
-	mcSHOW_DBG_MSG(("<<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL\n"));
+	msg("<<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL\n");
 }
 
 static void ANA_ARPI_shuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg,ANA_DVFS_CORE_T *tr)
@@ -501,7 +501,7 @@ static void ANA_TX_nonshuffle_config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ6)		, P_Fld(0							 , B1_DQ6_RG_TX_ARDQ_DDR3_SEL_B1		) \
 																| P_Fld(!(a_cfg->LP45_APHY_COMB_EN)  , B1_DQ6_RG_TX_ARDQ_DDR4_SEL_B1		) \
 																| P_Fld(a_cfg->LP45_APHY_COMB_EN	 , B1_DQ6_RG_TX_ARDQ_LP4_SEL_B1 		));
-	mcSHOW_DBG_MSG(("<<<<<< [CONFIGURE PHASE]: ANA_TX\n"));
+	msg("<<<<<< [CONFIGURE PHASE]: ANA_TX\n");
 	//enable TX OE
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2)		, P_Fld(1					   , CA_CMD2_RG_TX_ARCMD_OE_DIS_CA		  ) \
 																| P_Fld(0					   , CA_CMD2_RG_TX_ARCMD_ODTEN_DIS_CA	  ) \
@@ -683,7 +683,7 @@ static void ANA_RX_nonshuffle_config(DRAMC_CTX_T *p)
 //============================================
 void RESETB_PULL_DN(DRAMC_CTX_T *p)
 {
-	mcSHOW_DBG_MSG(("============ PULL DRAM RESETB DOWN ============\n"));
+	msg("============ PULL DRAM RESETB DOWN ============\n");
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11)		, P_Fld( 1					   , CA_CMD11_RG_RRESETB_DRVP		  ) \
 																| P_Fld( 1					   , CA_CMD11_RG_RRESETB_DRVN		  ) \
 																| P_Fld( 1					   , CA_CMD11_RG_TX_RRESETB_DDR3_SEL  ) \
@@ -694,7 +694,7 @@ void RESETB_PULL_DN(DRAMC_CTX_T *p)
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL1)	, P_Fld( 1					   , MISC_CTRL1_R_DMDA_RRESETB_E	  ));
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD11)		, P_Fld( 0					   , CA_CMD11_RG_TX_RRESETB_PULL_DN   ));
-	mcSHOW_DBG_MSG(("========== PULL DRAM RESETB DOWN end =========\n"));
+	msg("========== PULL DRAM RESETB DOWN end =========\n");
 }
 //============================================
 // SUSPEND_OFF_control
@@ -944,16 +944,16 @@ static void ANA_PHY_Config(DRAMC_CTX_T *p,ANA_top_config_T *a_cfg)
 
 static void ANA_PLL_sequence(DRAMC_CTX_T *p)
 {
-	mcSHOW_DBG_MSG(("[ANA_INIT] PLL >>>>>>>> \n"));
+	msg("[ANA_INIT] PLL >>>>>>>> \n");
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL2)	 , P_Fld(1, PHYPLL2_RG_RPHYPLL_RESETB				 ));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_PHYPLL0)	 , P_Fld(1, PHYPLL0_RG_RPHYPLL_EN					 ));
 	mcDELAY_XUS(20);
-	mcSHOW_DBG_MSG(("[ANA_INIT] PLL <<<<<<<< \n"));
+	msg("[ANA_INIT] PLL <<<<<<<< \n");
 }
 
 static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
 {
-	mcSHOW_DBG_MSG(("[ANA_INIT] MIDPI >>>>>>>> \n"));
+	msg("[ANA_INIT] MIDPI >>>>>>>> \n");
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1)   , 1, SHU_B0_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B0   );
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ1)   , 1, SHU_B1_DQ1_RG_ARPI_MIDPI_LDO_VREF_SEL_B1   );
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD1)  , 1, SHU_CA_CMD1_RG_ARPI_MIDPI_LDO_VREF_SEL_CA	);
@@ -1054,7 +1054,7 @@ static void ANA_MIDPI_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr)
 				| P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_CG_CLKIEN)
 				| P_Fld(0x0, SHU_CA_DLL_ARPI2_RG_ARPI_MPDIV_CG_CA));
 
-	mcSHOW_DBG_MSG(("[ANA_INIT] MIDPI <<<<<<<< \n"));
+	msg("[ANA_INIT] MIDPI <<<<<<<< \n");
 }
 
 static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
@@ -1065,7 +1065,7 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
 	DLL_ASYNC_EN = a_cfg->DLL_ASYNC_EN;
 	ALL_SLAVE_EN = a_cfg->ALL_SLAVE_EN;
 
-	mcSHOW_DBG_MSG(("[ANA_INIT] DLL >>>>>>>> \n"));
+	msg("[ANA_INIT] DLL >>>>>>>> \n");
 	//step1: DLL_RESETB
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD8)			 , P_Fld(  1		 , CA_CMD8_RG_ARDLL_RESETB_CA ));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ8)			 , P_Fld(  1		 , B0_DQ8_RG_ARDLL_RESETB_B0  ));
@@ -1111,7 +1111,7 @@ static void ANA_DLL_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T
 		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DLL1)		 , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0		 ));
 		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DLL1)		 , P_Fld(!(tr->DQ_SEMI_OPEN), SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1		 ));
 		mcDELAY_XNS(400); //2nd DLL > 77TMCK
-	mcSHOW_DBG_MSG(("[ANA_INIT] DLL <<<<<<<< \n"));
+	msg("[ANA_INIT] DLL <<<<<<<< \n");
 	}
 }
 
@@ -1209,18 +1209,18 @@ static void ANA_ClockOff_Sequence(DRAMC_CTX_T *p)
 
 static void ANA_init_sequence(DRAMC_CTX_T *p,ANA_DVFS_CORE_T *tr,ANA_top_config_T *a_cfg)
 {
-	mcSHOW_DBG_MSG(("[ANA_INIT] flow start \n"));
+	msg("[ANA_INIT] flow start \n");
 	ANA_PLL_sequence(p);
 	ANA_MIDPI_sequence(p,tr);
 	ANA_CLOCK_SWITCH(p); //clock switch supply correct FB clk. have to do this before DLL
 	ANA_DLL_sequence(p,tr,a_cfg);
-	mcSHOW_DBG_MSG(("[ANA_INIT] flow end \n"));
+	msg("[ANA_INIT] flow end \n");
 }
 
 void ANA_init(DRAMC_CTX_T *p)
 {
 	DRAMC_SUBSYS_PRE_CONFIG(p, &DV_p);
-	mcSHOW_DBG_MSG(("[ANA_INIT] >>>>>>>>>>>>>> \n"));
+	msg("[ANA_INIT] >>>>>>>>>>>>>> \n");
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_CA_CMD2), P_Fld(1, CA_CMD2_RG_TX_ARCMD_OE_DIS_CA)
 													| P_Fld(0, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA)
 													| P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA));
@@ -1231,7 +1231,7 @@ void ANA_init(DRAMC_CTX_T *p)
 											| P_Fld(1, CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA)
 											| P_Fld(0xff, CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA));
 	LP4_single_end_DRAMC_post_config(p, M_LP4->LP4Y_EN);
-	mcSHOW_DBG_MSG(("[ANA_INIT] <<<<<<<<<<<<< \n"));
+	msg("[ANA_INIT] <<<<<<<<<<<<< \n");
 }
 
 #if 0
diff --git a/src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c b/src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c
index 05a0f05570..7760271e9f 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/DIG_NONSHUF_config.c
@@ -15,7 +15,7 @@ static void DIG_PHY_config(DRAMC_CTX_T *p)
 	U8 RK_SWAP_EN = 0;
 #endif
 
-	mcSHOW_DBG_MSG(("[Flow] Enable top DCM control >>>>> \n"));
+	msg("[Flow] Enable top DCM control >>>>> \n");
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) 		 , P_Fld(	3	  , MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL		));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CG_CTRL2) 		 , P_Fld(	0	  , MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG		) \
 																		 | P_Fld(	0x1f  , MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL		));
@@ -33,9 +33,9 @@ static void DIG_PHY_config(DRAMC_CTX_T *p)
 																		 | P_Fld(	1	  , MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF		));
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RXDVS2)			 , P_Fld(	1	  , MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG));
-	mcSHOW_DBG_MSG(("[Flow] Enable top DCM control <<<<< \n"));
+	msg("[Flow] Enable top DCM control <<<<< \n");
 
-	mcSHOW_DBG_MSG(("Enable DLL master slave shuffle \n"));
+	msg("Enable DLL master slave shuffle \n");
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFS_EMI_CLK) 	 , P_Fld(	1	  , MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY ));
 
@@ -85,21 +85,21 @@ static void GATING_MODE_CFG(Gating_confg_T *tr)
 	tr->SELPH_MODE			 = 1; //random inside {0,1} //for improve APHY XRTR2R. NEW_APHY MODE with 1.
 	tr->VALID_LAT_VALUE 	 = 1; //random inside {0,1}
 
-	mcSHOW_DBG_MSG(("============================================================== \n"));
-	mcSHOW_DBG_MSG(("Gating Mode config\n"				));
-	mcSHOW_DBG_MSG(("============================================================== \n"));
-	mcSHOW_DBG_MSG(("Config description: \n"));
-	mcSHOW_DBG_MSG(("RX_GATING_MODE 	   0: Pulse Mode	  1: Burst Mode(8UI)		2: Burst Mode(7UI)	3: Original Burst Mode\n"));
-	mcSHOW_DBG_MSG(("RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode\n"));
-	mcSHOW_DBG_MSG(("SELPH_MODE 		   0: By rank		  1: By Phase \n"));
-	mcSHOW_DBG_MSG(("============================================================== \n"));
-	mcSHOW_DBG_MSG(("GAT_TRACK_EN				  = %2d\n",tr->GAT_TRACK_EN 	   ));
-	mcSHOW_DBG_MSG(("RX_GATING_MODE 			  = %2d\n",tr->RX_GATING_MODE	   ));
-	mcSHOW_DBG_MSG(("RX_GATING_TRACK_MODE		  = %2d\n",tr->RX_GATING_TRACK_MODE));
-	mcSHOW_DBG_MSG(("SELPH_MODE 				  = %2d\n",tr->SELPH_MODE		   ));
-	mcSHOW_DBG_MSG(("PICG_EARLY_EN				  = %2d\n",tr->PICG_EARLY_EN	   ));
-	mcSHOW_DBG_MSG(("VALID_LAT_VALUE			  = %2d\n",tr->VALID_LAT_VALUE	   ));
-	mcSHOW_DBG_MSG(("============================================================== \n"));
+	msg("============================================================== \n");
+	msg("Gating Mode config\n"				);
+	msg("============================================================== \n");
+	msg("Config description: \n");
+	msg("RX_GATING_MODE 	   0: Pulse Mode	  1: Burst Mode(8UI)		2: Burst Mode(7UI)	3: Original Burst Mode\n");
+	msg("RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode\n");
+	msg("SELPH_MODE 		   0: By rank		  1: By Phase \n");
+	msg("============================================================== \n");
+	msg("GAT_TRACK_EN				  = %2d\n",tr->GAT_TRACK_EN 	   );
+	msg("RX_GATING_MODE 			  = %2d\n",tr->RX_GATING_MODE	   );
+	msg("RX_GATING_TRACK_MODE		  = %2d\n",tr->RX_GATING_TRACK_MODE);
+	msg("SELPH_MODE 				  = %2d\n",tr->SELPH_MODE		   );
+	msg("PICG_EARLY_EN				  = %2d\n",tr->PICG_EARLY_EN	   );
+	msg("VALID_LAT_VALUE			  = %2d\n",tr->VALID_LAT_VALUE	   );
+	msg("============================================================== \n");
 }
 
 //======================================
@@ -107,7 +107,7 @@ static void GATING_MODE_CFG(Gating_confg_T *tr)
 //======================================
 static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
 {
-	mcSHOW_DBG_MSG(("Enter into Gating configuration >>>> \n"));
+	msg("Enter into Gating configuration >>>> \n");
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1)		, P_Fld(!gat_c->GAT_TRACK_EN, MISC_STBCAL1_STBCNT_SW_RST		  ));
 
@@ -169,7 +169,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
 		}
 		default:
 		{
-			mcSHOW_DBG_MSG(("ERROR: Gating Mode choose unexpected Mode!!!!\n"));
+			msg("ERROR: Gating Mode choose unexpected Mode!!!!\n");
 			break;
 		}
 	}
@@ -269,7 +269,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
 		}
 		default:
 		{
-			mcSHOW_DBG_MSG(("ERROR: Gating tracking Mode choose unexpected Mode!!!!"));
+			msg("ERROR: Gating tracking Mode choose unexpected Mode!!!!");
 			break;
 		}
 	}
@@ -298,7 +298,7 @@ static void DPHY_GAT_TRACK_Config(DRAMC_CTX_T *p,Gating_confg_T *gat_c)
 																	| P_Fld(   1  , MISC_STBCAL2_STB_RST_BY_RANK				) \
 																	| P_Fld(   1  , MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN		));
 	}
-	mcSHOW_DBG_MSG(("Exit from Gating configuration <<<< \n"));
+	msg("Exit from Gating configuration <<<< \n");
 }
 
 static void RX_INTPUT_Config(DRAMC_CTX_T *p)
@@ -319,7 +319,7 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p)
 
 	backup_rank = p->rank;
 
-	mcSHOW_DBG_MSG(("[RX_INPUT] configuration >>>>> \n"));
+	msg("[RX_INPUT] configuration >>>>> \n");
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_RXDVS0) 	 , P_Fld(  1   , B0_RXDVS0_R_HWSAVE_MODE_ENA_B0 						   ) \
 																 | P_Fld(  0   , B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0						   ) \
@@ -428,7 +428,7 @@ static void RX_INTPUT_Config(DRAMC_CTX_T *p)
 //		  `TBA_TOP.dvfs_spm_vif.sc_dphy_reserved[1:0] = 2'b11; //TODO
 	}
 
-	mcSHOW_DBG_MSG(("[RX_INPUT] configuration <<<<< \n"));
+	msg("[RX_INPUT] configuration <<<<< \n");
 }
 
 static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
@@ -437,7 +437,7 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
 	U8 MISC_CG_EN = 1;
 	U8 MISC_CG_REVERSE_DEFAULT_ON = 0;	//for default CG enable.
 
-	mcSHOW_DBG_MSG(("Enter into PICG configuration >>>> \n"));
+	msg("Enter into PICG configuration >>>> \n");
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4)		, P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_MPDIV_CG					) \
 																	| P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_CG_MCK					) \
 																	| P_Fld(   PICG_MODE  , MISC_CTRL4_R_OPT2_CG_DQM					) \
@@ -530,7 +530,7 @@ static void DDRPHY_PICG_Config(DRAMC_CTX_T *p)
 																		| P_Fld(   1	  , SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1		 ));
 	}
 
-	mcSHOW_DBG_MSG(("Exit from PICG configuration <<<< \n"));
+	msg("Exit from PICG configuration <<<< \n");
 }
 
 static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
@@ -551,7 +551,7 @@ static void DRAMC_COMMON_Config(DRAMC_CTX_T *p)
 		RUNTIME_MRR   = 1;
 	} else {
 		//TODO
-		mcSHOW_DBG_MSG(("NONBLOCKALE RUNTIMEMRR could be random.--for MP should setting 1. just record it."));
+		msg("NONBLOCKALE RUNTIMEMRR could be random.--for MP should setting 1. just record it.");
 	}
 
 
@@ -836,7 +836,7 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p)
 #endif
 	U32 REF_104M_EN = 1;
 	DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
-	mcSHOW_DBG_MSG(("Enter into  DVFS_PRE_config >>>>> \n"));
+	msg("Enter into  DVFS_PRE_config >>>>> \n");
 
 #if ENABLE_ECO_SRAM_DMA_MISS_REG
 	vIO32WriteFldMulti_All(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ11  )  , P_Fld( 1 	, B0_DQ11_DMY_DQ11_B0					));
@@ -904,7 +904,7 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p)
 																	| P_Fld((REF_104M_EN==1)?3:1, MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW			) );
 	if(A_T->DLL_ASYNC_EN == 0)
 	{
-		mcSHOW_DBG_MSG(("Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. \n"));
+		msg("Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. \n");
 		//DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
 		vSetPHY2ChannelMapping(p, CHANNEL_B);
 		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL2	 )	, P_Fld(   0			 , MISC_DVFSCTL2_R_DVFS_DLL_CHA 				 ));
@@ -923,12 +923,12 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p)
 	{
 		//DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
 		vSetPHY2ChannelMapping(p, CHANNEL_B);
-		mcSHOW_DBG_MSG(("MCP Enable leading 2ch's sync singles should adjust delay margin."));
+		msg("MCP Enable leading 2ch's sync singles should adjust delay margin.");
 		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL	 )	, P_Fld((REF_104M_EN==1)?6:4, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW		 ));
 		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3	)	, P_Fld(   9				, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK    ));
 		#if (CHANNEL_NUM>2)
 		vSetPHY2ChannelMapping(p, CHANNEL_D);
-		mcSHOW_DBG_MSG(("MCP Enable leading 2ch's sync singles should adjust delay margin."));
+		msg("MCP Enable leading 2ch's sync singles should adjust delay margin.");
 		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL	 )	, P_Fld((REF_104M_EN==1)?6:4, MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW		 ));
 		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DVFSCTL3	)	, P_Fld(   9				, MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK    ));
 		#endif
@@ -957,7 +957,7 @@ static void DVFS_PRE_config(DRAMC_CTX_T *p)
 	#endif
 	vSetPHY2ChannelMapping(p, CHANNEL_A);
 	DramcBroadcastOnOff(DRAMC_BROADCAST_ON);
-	mcSHOW_DBG_MSG(("Exit from	DVFS_PRE_config <<<<< \n"));
+	msg("Exit from	DVFS_PRE_config <<<<< \n");
 }
 
 void DIG_STATIC_SETTING(DRAMC_CTX_T *p)
diff --git a/src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c b/src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c
index b5dfe2f2aa..a99b3345ab 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/DIG_SHUF_config.c
@@ -11,7 +11,7 @@
 //====================================
 static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
 {
-	mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
+	msg("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id);
 
 	U8 backup_ch_id = p->channel;
 	u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
@@ -90,7 +90,7 @@ static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
 	vSetPHY2ChannelMapping(p, backup_ch_id);
 	p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
 
-	mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
+	msg("[DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id);
 }
 
 //====================================
@@ -101,7 +101,7 @@ static void DIG_CONFIG_SHUF_ALG_TXCA(DRAMC_CTX_T *p, int ch_id, int group_id)
 //====================================
 static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id)
 {
-	mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
+	msg("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id);
 	U8	IPM_ODT_EN;
 	U8	CHKCYCLE	  = 7; //200ns algrith --TODO, @Darren, fix hw imp tracking
 	U8	TXDLY_CMD	  = 8; //Need algrithm support .. RL . TODO
@@ -131,7 +131,7 @@ static void DIG_CONFIG_SHUF_IMP(DRAMC_CTX_T *p, int ch_id, int group_id)
 
 	vSetPHY2ChannelMapping(p, backup_ch_id);
 	p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
-	mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
+	msg("[DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id);
 }
 
 //====================================
@@ -152,7 +152,7 @@ static void DIG_CONFIG_SHUF_RXINPUT(DRAMC_CTX_T *p, int ch_id, int group_id)
 	vSetPHY2ChannelMapping(p, ch_id);
 	p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
 
-	mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id));
+	msg("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d >>>>>\n", ch_id, group_id);
 	if(RX_force_upd == 1)
 	{
 		vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ8), P_Fld(1, SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0));
@@ -173,7 +173,7 @@ static void DIG_CONFIG_SHUF_RXINPUT(DRAMC_CTX_T *p, int ch_id, int group_id)
 	vSetPHY2ChannelMapping(p, backup_ch_id);
 	p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
 
-	mcSHOW_DBG_MSG(("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id));
+	msg("[DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id:%2d, group_id:%2d <<<<<\n", ch_id, group_id);
 }
 
 #if ENABLE_WDQS_MODE_2
@@ -197,7 +197,7 @@ static void WDQSMode2TxDQOE_CNT(DRAMC_CTX_T *p, U8 *u1DQOE_CNT)
 			*u1DQOE_CNT = 9;
 			break;
 		default:
-			mcSHOW_ERR_MSG(("[WDQSMode2TxDQOE_CNT] frequency err!\n"));
+			err("[WDQSMode2TxDQOE_CNT] frequency err!\n");
 			#if __ETT__
 			while (1);
 			#endif
@@ -232,7 +232,7 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
 
 	backup_rank = p->rank;
 
-	mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] MISC >>>>>, group_id=%2d \n", group_id));
+	msg("[DIG_SHUF_CONFIG] MISC >>>>>, group_id=%2d \n", group_id);
 	if(LPDDR4_EN_S)
 	{
 		DUALSCHEN = (A_D->DQ_P2S_RATIO==4) ? 0 : 1;
@@ -250,7 +250,7 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
 		case 3: {DQSIEN_DQSSTB_MODE = 3;break;}
 		case 6: {DQSIEN_DQSSTB_MODE = 2;break;}
 		case 7: {DQSIEN_DQSSTB_MODE = 3;break;}
-		default: mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] Unexpected DFS(group_id)->DQSIEN_MODE=%1d input, group_id=%2d, \n",DFS(group_id)->DQSIEN_MODE, group_id));
+		default: msg("[DIG_SHUF_CONFIG] Unexpected DFS(group_id)->DQSIEN_MODE=%1d input, group_id=%2d, \n",DFS(group_id)->DQSIEN_MODE, group_id);
 	}
 
 	switch(LP5_CASMODE)
@@ -258,7 +258,7 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
 		case 1: {WCKDUAL=0;LP5_HEFF=0;break;}
 		case 2: {WCKDUAL=1;LP5_HEFF=0;break;}
 		case 3: {WCKDUAL=0;LP5_HEFF=1;break;}
-		default: mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] Unexpected LP5_CASMODE(%d) input\n",LP5_CASMODE));
+		default: msg("[DIG_SHUF_CONFIG] Unexpected LP5_CASMODE(%d) input\n",LP5_CASMODE);
 	}
 
 
@@ -377,14 +377,14 @@ static void DIG_CONFIG_SHUF_MISC_FIX(DRAMC_CTX_T *p,U32 ch_id, U32 group_id)
 																				| P_Fld( 0			, MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT		 ));
 			break;
 		}
-		default:mcSHOW_DBG_MSG(("ERROR:Unexcepted A_D.DQ_P2S_RATIO = %2d \n", A_D->DQ_P2S_RATIO));
+		default:msg("ERROR:Unexcepted A_D.DQ_P2S_RATIO = %2d \n", A_D->DQ_P2S_RATIO);
 	}
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_CKE_CTRL) 				, P_Fld(  0 		, SHURK_CKE_CTRL_CKE_DBE_CNT				 ));
 
 	vSetPHY2ChannelMapping(p, backup_ch_id);
 	p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
 
-	mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] MISC <<<<<<, group_id=%2d \n", group_id));
+	msg("[DIG_SHUF_CONFIG] MISC <<<<<<, group_id=%2d \n", group_id);
 }
 
 static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id)
@@ -393,7 +393,7 @@ static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id)
 	u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
 
 	vSetPHY2ChannelMapping(p, ch_id);
-	mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id=%2d \n", group_id));
+	msg("[DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id=%2d \n", group_id);
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_DQSG_RETRY1), P_Fld( 0								, MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET		 ) \
 																	  | P_Fld( 0								, MISC_SHU_DQSG_RETRY1_RETRY_SW_EN			 ) \
 																	  | P_Fld( (DFS(group_id)->data_rate>=3733) , MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS	 ) \
@@ -419,7 +419,7 @@ static void DIG_CONFIG_SHUF_DQSGRETRY(DRAMC_CTX_T *p, int ch_id, int group_id)
 
 	vSetPHY2ChannelMapping(p, backup_ch_id);
 	p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
-	mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id=%2d \n", group_id));
+	msg("[DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id=%2d \n", group_id);
 }
 
 static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
@@ -433,7 +433,7 @@ static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
 	U8 backup_ch_id = p->channel;
 	u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
 
-	mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DBI >>>>>>, group_id=%2d \n",  group_id));
+	msg("[DIG_SHUF_CONFIG] DBI >>>>>>, group_id=%2d \n",  group_id);
 	if(LPDDR4_EN_S)
 	{
 		LP4_DRAM_config(DFS(group_id)->data_rate,&LP4_temp);
@@ -459,7 +459,7 @@ static void DIG_CONFIG_SHUF_DBI(DRAMC_CTX_T *p, int ch_id, int group_id)
 
 	vSetPHY2ChannelMapping(p, backup_ch_id);
 	p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
-	mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DBI <<<<<<, group_id=%2d \n",  group_id));
+	msg("[DIG_SHUF_CONFIG] DBI <<<<<<, group_id=%2d \n",  group_id);
 }
 
 //TODO LPDDR5
@@ -474,7 +474,7 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
 	U8	HWSET_VRCG_OP_Value   =0;
 	U8	HWSET_MR2_OP_Value	  =0;
 
-	mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id=%2d \n",  group_id));
+	msg("[DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id=%2d \n",  group_id);
 	p->ShuRGAccessIdx = (group_id == 0) ? DRAM_DFS_REG_SHU0 : DRAM_DFS_REG_SHU1;
 
 	if(LPDDR4_EN_S)
@@ -485,7 +485,7 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
 		HWSET_VRCG_OP_Value = ((LP4_temp.WORK_FSP & 1) << 7) | ((LP4_temp.WORK_FSP & 1) << 6);
 		HWSET_MR2_OP_Value	= ((LP4_temp.MR_WL & 7) << 3) | (LP4_temp.MR_WL & 7);
 	} else {
-		mcSHOW_DBG_MSG(("[DIG_SHUF_CONFIG] LPDDR5 have to use Run-time MRW to support DVFS! Do not Use HWSET_MR serial Registers."));
+		msg("[DIG_SHUF_CONFIG] LPDDR5 have to use Run-time MRW to support DVFS! Do not Use HWSET_MR serial Registers.");
 	}
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_HWSET_MR13), P_Fld(HWSET_MR13_OP_Value, SHU_HWSET_MR13_HWSET_MR13_OP ));
@@ -495,7 +495,7 @@ static void DIG_CONFIG_SHUF_DVFSWLRL(DRAMC_CTX_T *p, int ch_id, int group_id)
 	vSetPHY2ChannelMapping(p, backup_ch_id);
 	p->ShuRGAccessIdx = backup_ShuRGAccessIdx;
 
-	mcSHOW_DBG_MSG(("[test_sa.c]====>ch_id:%2d, group_id:%2d, DPI_TBA_DVFS_WLRL_setting Exit\n", ch_id, group_id));
+	msg("[test_sa.c]====>ch_id:%2d, group_id:%2d, DPI_TBA_DVFS_WLRL_setting Exit\n", ch_id, group_id);
 }
 
 //=================================================
@@ -516,7 +516,7 @@ void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id)
 	u8 backup_ShuRGAccessIdx = p->ShuRGAccessIdx;
 
 	vSetPHY2ChannelMapping(p, ch_id);
-	mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]>>>>>>>> group_id = %1d",group_id));
+	msg("[TX_RX_jumpratio_calculate]>>>>>>>> group_id = %1d",group_id);
 	for(tar = 0; tar<DFS_GROUP_NUM;tar++)
 	{
 		if(((DFS(group_id)->data_rate == 800) || (DFS(group_id)->data_rate == 400)) || ((DFS(tar)->data_rate == 800) || (DFS(tar)->data_rate == 400))) //TODO wihtout tracking
@@ -527,7 +527,7 @@ void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id)
 		{
 			result[tar] = (int)(((float)(DFS(tar)->data_rate) * (float)ratio) / (float)(DFS(group_id)->data_rate) + 0.5); //+0.5 for roundup
 		}
-		mcSHOW_DBG_MSG(("\n[TXRX_jumpratio]current_group data_rate=%1d,tar_data_rate=%1d,jumpratio=%1d;\n",DFS(group_id)->data_rate,DFS(tar)->data_rate,result[tar]));
+		msg("\n[TXRX_jumpratio]current_group data_rate=%1d,tar_data_rate=%1d,jumpratio=%1d;\n",DFS(group_id)->data_rate,DFS(tar)->data_rate,result[tar]);
 	}
 	//=============================
 	//setting
@@ -546,7 +546,7 @@ void TX_RX_jumpratio_calculate(DRAMC_CTX_T *p,int ch_id,int group_id)
 																	| P_Fld(   result[9]  , SHU_FREQ_RATIO_SET2_TDQSCK_JUMP_RATIO9));
 	vSetPHY2ChannelMapping(p, backup_ch_id);
 	p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
-	mcSHOW_DBG_MSG(("[TX_RX_jumpratio_calculate]<<<<<<< group_id = %1d",group_id));
+	msg("[TX_RX_jumpratio_calculate]<<<<<<< group_id = %1d",group_id);
 }
 #endif
 
diff --git a/src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c b/src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c
index 8e1e332335..885eec55e9 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/DRAMC_SUBSYS_config.c
@@ -29,17 +29,17 @@ void ANA_TOP_FUNCTION_CFG(ANA_top_config_T *tr,U16 data_rate)
 		tr->TX_ODT_DIS = (data_rate <=2400) ? 1 : 0 ;
 	}
 
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("ANA top config\n"				));
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("DLL_ASYNC_EN			 = %2d\n",tr->DLL_ASYNC_EN	   ));
-	mcSHOW_DBG_MSG(("ALL_SLAVE_EN			 = %2d\n",tr->ALL_SLAVE_EN	   ));
-	mcSHOW_DBG_MSG(("NEW_RANK_MODE			 = %2d\n",tr->NEW_RANK_MODE    ));
-	mcSHOW_DBG_MSG(("DLL_IDLE_MODE			 = %2d\n",tr->DLL_IDLE_MODE    ));
-	mcSHOW_DBG_MSG(("LP45_APHY_COMB_EN		 = %2d\n",tr->LP45_APHY_COMB_EN));
-	mcSHOW_DBG_MSG(("TX_ODT_DIS 			 = %2d\n",tr->TX_ODT_DIS	   ));
-	mcSHOW_DBG_MSG(("NEW_8X_MODE			 = %2d\n",tr->NEW_8X_MODE	   ));
-	mcSHOW_DBG_MSG(("=================================== \n"));
+	msg("=================================== \n");
+	msg("ANA top config\n"				);
+	msg("=================================== \n");
+	msg("DLL_ASYNC_EN			 = %2d\n",tr->DLL_ASYNC_EN	   );
+	msg("ALL_SLAVE_EN			 = %2d\n",tr->ALL_SLAVE_EN	   );
+	msg("NEW_RANK_MODE			 = %2d\n",tr->NEW_RANK_MODE    );
+	msg("DLL_IDLE_MODE			 = %2d\n",tr->DLL_IDLE_MODE    );
+	msg("LP45_APHY_COMB_EN		 = %2d\n",tr->LP45_APHY_COMB_EN);
+	msg("TX_ODT_DIS 			 = %2d\n",tr->TX_ODT_DIS	   );
+	msg("NEW_8X_MODE			 = %2d\n",tr->NEW_8X_MODE	   );
+	msg("=================================== \n");
 }
 
 
@@ -123,32 +123,32 @@ void ANA_CLK_DIV_config( ANA_DVFS_CORE_T *tr,DRAMC_DVFS_GROUP_CONFIG_T *dfs)
 	tr->DQ_UI_PI_RATIO = 32; //TODO:notice here. infact if DQ_SEMI_OPEM == 1 UI_PI_RATIO will only 4 lower 2bit wihtout use
 	tr->CA_UI_PI_RATIO = (tr->CA_SEMI_OPEN == 0) ? ((tr->CA_FULL_RATE == 1)? 64 : DONT_CARE_VALUE) : 32;
 
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("data_rate					= %4d\n"	,data_rate						));
-	mcSHOW_DBG_MSG(("CKR						= %1d\n"	,tr->CKR						));
-	mcSHOW_DBG_MSG(("DQ_P2S_RATIO				= %1d\n"	,tr->DQ_P2S_RATIO				));
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("CA_P2S_RATIO				= %1d\n"	,tr->CA_P2S_RATIO				));
-	mcSHOW_DBG_MSG(("DQ_CA_OPEN 				= %1d\n"	,tr->DQ_CA_OPEN 				));
-	mcSHOW_DBG_MSG(("DQ_SEMI_OPEN				= %1d\n"	,tr->DQ_SEMI_OPEN				));
-	mcSHOW_DBG_MSG(("CA_SEMI_OPEN				= %1d\n"	,tr->CA_SEMI_OPEN				));
-	mcSHOW_DBG_MSG(("CA_FULL_RATE				= %1d\n"	,tr->CA_FULL_RATE				));
-	mcSHOW_DBG_MSG(("DQ_CKDIV4_EN				= %1d\n"	,tr->DQ_CKDIV4_EN				));
-	mcSHOW_DBG_MSG(("CA_CKDIV4_EN				= %1d\n"	,tr->CA_CKDIV4_EN				));
-	mcSHOW_DBG_MSG(("CA_PREDIV_EN				= %1d\n"	,tr->CA_PREDIV_EN				));
-	mcSHOW_DBG_MSG(("PH8_DLY					= %1d\n"	,tr->PH8_DLY					));
-	mcSHOW_DBG_MSG(("SEMI_OPEN_CA_PICK_MCK_RATIO= %1d\n"	,tr->SEMI_OPEN_CA_PICK_MCK_RATIO));
-	mcSHOW_DBG_MSG(("DQ_AAMCK_DIV				= %1d\n"	,tr->DQ_AAMCK_DIV				));
-	mcSHOW_DBG_MSG(("CA_AAMCK_DIV				= %1d\n"	,tr->CA_AAMCK_DIV				));
-	mcSHOW_DBG_MSG(("CA_ADMCK_DIV				= %1d\n"	,tr->CA_ADMCK_DIV				));
-	mcSHOW_DBG_MSG(("DQ_TRACK_CA_EN 			= %1d\n"	,tr->DQ_TRACK_CA_EN 			));
-	mcSHOW_DBG_MSG(("CA_PICK					= %2d\n"	,CA_PICK						));
-	mcSHOW_DBG_MSG(("CA_MCKIO					= %1d\n"	,CA_MCKIO						));
-	mcSHOW_DBG_MSG(("MCKIO_SEMI 				= %1d\n"	,MCKIO_SEMI 					));
-	mcSHOW_DBG_MSG(("PLL_FREQ					= %1d\n"	,tr->PLL_FREQ					));
-	mcSHOW_DBG_MSG(("DQ_UI_PI_RATIO 			= %1d\n"	,tr->DQ_UI_PI_RATIO 			));
-	mcSHOW_DBG_MSG(("CA_UI_PI_RATIO 			= %1d\n"	,tr->CA_UI_PI_RATIO 			));
-	mcSHOW_DBG_MSG(("=================================== \n"));
+	msg("=================================== \n");
+	msg("data_rate					= %4d\n"	,data_rate						);
+	msg("CKR						= %1d\n"	,tr->CKR						);
+	msg("DQ_P2S_RATIO				= %1d\n"	,tr->DQ_P2S_RATIO				);
+	msg("=================================== \n");
+	msg("CA_P2S_RATIO				= %1d\n"	,tr->CA_P2S_RATIO				);
+	msg("DQ_CA_OPEN 				= %1d\n"	,tr->DQ_CA_OPEN 				);
+	msg("DQ_SEMI_OPEN				= %1d\n"	,tr->DQ_SEMI_OPEN				);
+	msg("CA_SEMI_OPEN				= %1d\n"	,tr->CA_SEMI_OPEN				);
+	msg("CA_FULL_RATE				= %1d\n"	,tr->CA_FULL_RATE				);
+	msg("DQ_CKDIV4_EN				= %1d\n"	,tr->DQ_CKDIV4_EN				);
+	msg("CA_CKDIV4_EN				= %1d\n"	,tr->CA_CKDIV4_EN				);
+	msg("CA_PREDIV_EN				= %1d\n"	,tr->CA_PREDIV_EN				);
+	msg("PH8_DLY					= %1d\n"	,tr->PH8_DLY					);
+	msg("SEMI_OPEN_CA_PICK_MCK_RATIO= %1d\n"	,tr->SEMI_OPEN_CA_PICK_MCK_RATIO);
+	msg("DQ_AAMCK_DIV				= %1d\n"	,tr->DQ_AAMCK_DIV				);
+	msg("CA_AAMCK_DIV				= %1d\n"	,tr->CA_AAMCK_DIV				);
+	msg("CA_ADMCK_DIV				= %1d\n"	,tr->CA_ADMCK_DIV				);
+	msg("DQ_TRACK_CA_EN 			= %1d\n"	,tr->DQ_TRACK_CA_EN 			);
+	msg("CA_PICK					= %2d\n"	,CA_PICK						);
+	msg("CA_MCKIO					= %1d\n"	,CA_MCKIO						);
+	msg("MCKIO_SEMI 				= %1d\n"	,MCKIO_SEMI 					);
+	msg("PLL_FREQ					= %1d\n"	,tr->PLL_FREQ					);
+	msg("DQ_UI_PI_RATIO 			= %1d\n"	,tr->DQ_UI_PI_RATIO 			);
+	msg("CA_UI_PI_RATIO 			= %1d\n"	,tr->CA_UI_PI_RATIO 			);
+	msg("=================================== \n");
 }
 
 void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
@@ -311,10 +311,10 @@ void DRAMC_SUBSYS_PRE_CONFIG(DRAMC_CTX_T *p, DRAMC_SUBSYS_CONFIG_T *tr)
 	ANA_TOP_FUNCTION_CFG(tr->a_cfg,tr->DFS_GP[0]->data_rate);
 	ANA_CLK_DIV_config(tr->a_opt,tr->DFS_GP[0]);
 
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("memory_type:%s 		\n",LPDDR5_EN_S?"LPDDR5":"LPDDR4"	  ));
-	mcSHOW_DBG_MSG(("GP_NUM 	: %1d		\n",tr->GP_NUM		));
-	mcSHOW_DBG_MSG(("SRAM_EN	: %1d		\n",tr->SRAM_EN 	));
-	mcSHOW_DBG_MSG(("MD32_EN	: %1d		\n",tr->MD32_EN 	));
-	mcSHOW_DBG_MSG(("=================================== \n"));
+	msg("=================================== \n");
+	msg("memory_type:%s 		\n",LPDDR5_EN_S?"LPDDR5":"LPDDR4"	  );
+	msg("GP_NUM 	: %1d		\n",tr->GP_NUM		);
+	msg("SRAM_EN	: %1d		\n",tr->SRAM_EN 	);
+	msg("MD32_EN	: %1d		\n",tr->MD32_EN 	);
+	msg("=================================== \n");
 }
diff --git a/src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c b/src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c
index 01a0569bb0..e7e2a9fcf1 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/DRAM_config_collctioin.c
@@ -39,26 +39,26 @@ void LP4_DRAM_config(U32 data_rate, LP4_DRAM_CONFIG_T *tr)
 	#endif
 	tr->WORK_FSP  = (data_rate>=2667)?1:0;
 
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("LPDDR4 DRAM CONFIGURATION\n"	  ));
-	mcSHOW_DBG_MSG(("=================================== \n"));
-//	  mcSHOW_DBG_MSG(("BYTE_MODE	= B%1b\n",tr->BYTE_MODE));
-	mcSHOW_DBG_MSG(("EX_ROW_EN[0]	 = 0x%1x\n",tr->EX_ROW_EN[0]));
-	mcSHOW_DBG_MSG(("EX_ROW_EN[1]	 = 0x%1x\n",tr->EX_ROW_EN[1]));
-	mcSHOW_DBG_MSG(("LP4Y_EN	  = 0x%1x\n",tr->LP4Y_EN  ));
-	mcSHOW_DBG_MSG(("WORK_FSP	  = 0x%1x\n",tr->WORK_FSP ));
-	mcSHOW_DBG_MSG(("WL 		  = 0x%1x\n",tr->MR_WL	  ));
-	mcSHOW_DBG_MSG(("RL 		  = 0x%1x\n",tr->MR_RL	  ));
-	mcSHOW_DBG_MSG(("BL 		  = 0x%1x\n",tr->BL 	  ));
-	mcSHOW_DBG_MSG(("RPST		  = 0x%1x\n",tr->RPST	  ));
-	mcSHOW_DBG_MSG(("RD_PRE 	  = 0x%1x\n",tr->RD_PRE   ));
-	mcSHOW_DBG_MSG(("WR_PRE 	  = 0x%1x\n",tr->WR_PRE   ));
-	mcSHOW_DBG_MSG(("WR_PST 	  = 0x%1x\n",tr->WR_PST   ));
-	mcSHOW_DBG_MSG(("DBI_WR 	  = 0x%1x\n",tr->DBI_WR   ));
-	mcSHOW_DBG_MSG(("DBI_RD 	  = 0x%1x\n",tr->DBI_RD   ));
-//	mcSHOW_DBG_MSG(("DMI		  = 0x%1x\n",tr->DMI	  ));
-	mcSHOW_DBG_MSG(("OTF		  = 0x%1x\n",tr->OTF	  ));
-	mcSHOW_DBG_MSG(("=================================== \n"));
+	msg("=================================== \n");
+	msg("LPDDR4 DRAM CONFIGURATION\n"	  );
+	msg("=================================== \n");
+//	  msg("BYTE_MODE	= B%1b\n",tr->BYTE_MODE);
+	msg("EX_ROW_EN[0]	 = 0x%1x\n",tr->EX_ROW_EN[0]);
+	msg("EX_ROW_EN[1]	 = 0x%1x\n",tr->EX_ROW_EN[1]);
+	msg("LP4Y_EN	  = 0x%1x\n",tr->LP4Y_EN  );
+	msg("WORK_FSP	  = 0x%1x\n",tr->WORK_FSP );
+	msg("WL 		  = 0x%1x\n",tr->MR_WL	  );
+	msg("RL 		  = 0x%1x\n",tr->MR_RL	  );
+	msg("BL 		  = 0x%1x\n",tr->BL 	  );
+	msg("RPST		  = 0x%1x\n",tr->RPST	  );
+	msg("RD_PRE 	  = 0x%1x\n",tr->RD_PRE   );
+	msg("WR_PRE 	  = 0x%1x\n",tr->WR_PRE   );
+	msg("WR_PST 	  = 0x%1x\n",tr->WR_PST   );
+	msg("DBI_WR 	  = 0x%1x\n",tr->DBI_WR   );
+	msg("DBI_RD 	  = 0x%1x\n",tr->DBI_RD   );
+//	msg("DMI		  = 0x%1x\n",tr->DMI	  );
+	msg("OTF		  = 0x%1x\n",tr->OTF	  );
+	msg("=================================== \n");
 }
 //LP4 dram initial ModeRegister setting
 U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
@@ -75,9 +75,9 @@ U8 LP4_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
 	else if ((data_rate<=1200) && (data_rate > 800 )) {MR2_RLWL = 2 ;}
 	else if ((data_rate<=800 ) && (data_rate > 400 )) {MR2_RLWL = 2 ;}
 	else if (data_rate<=400 )						  {MR2_RLWL = 0 ;}
-	else {mcSHOW_DBG_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR4 \n",data_rate));return -1;}
+	else {msg("ERROR: Unexpected data_rate:%4d under LPDDR4 \n",data_rate);return -1;}
 
-	mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
+	msg("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL);
 
 	return MR2_RLWL;
 }
@@ -96,10 +96,10 @@ U32 Get_RL_by_MR_LP4(U8 BYTE_MODE_EN,U8 DBI_EN, U8 MR_RL_field_value)
 		case 5: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 36 : 32 ) : ((DBI_EN == 1) ? 32 : 28); break;}
 		case 6: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 40 : 36 ) : ((DBI_EN == 1) ? 36 : 32); break;}
 		case 7: {RL = (BYTE_MODE_EN == 1) ? ((DBI_EN == 1) ? 44 : 40 ) : ((DBI_EN == 1) ? 40 : 36); break;}
-		default:{mcSHOW_DBG_MSG(("ERROR: Unexpected MR_RL_field_value:%1x under LPDDR4 \n",MR_RL_field_value));}
+		default:{msg("ERROR: Unexpected MR_RL_field_value:%1x under LPDDR4 \n",MR_RL_field_value);}
 	}
 
-	mcSHOW_DBG_MSG(("[ReadLatency GET] BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,RL));
+	msg("[ReadLatency GET] BYTE_MODE_EN:%1d-DBI_EN:%1d-MR_RL_field_value:%1x-RL:%2d\n",BYTE_MODE_EN,DBI_EN,MR_RL_field_value,RL);
 
 	return RL;
 }
@@ -118,10 +118,10 @@ U32 Get_WL_by_MR_LP4(U8 Version, U8 MR_WL_field_value)
 		case 5: {WL = ((Version == 0) ? 14 : 26 ); break;}
 		case 6: {WL = ((Version == 0) ? 16 : 30 ); break;}
 		case 7: {WL = ((Version == 0) ? 18 : 34 ); break;}
-		default:{mcSHOW_DBG_MSG(("ERROR: Unexpected MR_WL_field_value:%1x under LPDDR4 \n",MR_WL_field_value));}
+		default:{msg("ERROR: Unexpected MR_WL_field_value:%1x under LPDDR4 \n",MR_WL_field_value);}
 	}
 
-	mcSHOW_DBG_MSG(("[WriteLatency GET] Version:%1d-MR_RL_field_value:%1x-WL:%2d\n",Version,MR_WL_field_value,WL));
+	msg("[WriteLatency GET] Version:%1d-MR_RL_field_value:%1x-WL:%2d\n",Version,MR_WL_field_value,WL);
 
 	return WL;
 }
@@ -141,9 +141,9 @@ static U8 LP5_DRAM_INIT_RLWL_MRfield_config(U32 data_rate)
 	else if ((data_rate<=2400) && (data_rate > 1866)) {MR2_RLWL = 4  ;}
 	else if ((data_rate<=1866) && (data_rate > 1600)) {MR2_RLWL = 3  ;}
 	else if ((data_rate<=1600) && (data_rate >= 800)) {MR2_RLWL = 2  ;}
-	else {mcSHOW_DBG_MSG(("ERROR: Unexpected data_rate:%4d under LPDDR5 \n",data_rate));return -1;}
+	else {msg("ERROR: Unexpected data_rate:%4d under LPDDR5 \n",data_rate);return -1;}
 
-	mcSHOW_DBG_MSG(("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL));
+	msg("[ModeRegister RLWL Config] data_rate:%4d-MR2_RLWL:%1x\n",data_rate,MR2_RLWL);
 
 	return MR2_RLWL;
 }
@@ -209,42 +209,42 @@ void LP5_DRAM_config(DRAMC_DVFS_GROUP_CONFIG_T *dfs_tr, LP5_DRAM_CONFIG_T *tr)
 		case 3: {tr->RDQS_PRE = 3;break;}
 		case 6: {tr->RDQS_PRE = 1;break;}
 		case 7: {tr->RDQS_PRE = 3;break;}
-		default : {mcSHOW_DBG_MSG(("ERROR: Unexpected DQSIEN_MODE :%d \n",dfs_tr->DQSIEN_MODE)); while(1);};
+		default : {msg("ERROR: Unexpected DQSIEN_MODE :%d \n",dfs_tr->DQSIEN_MODE); while(1);};
 	}
 
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("LPDDR5 DRAM CONFIGURATION\n"	  ));
-	mcSHOW_DBG_MSG(("=================================== \n"));
-	mcSHOW_DBG_MSG(("MR_WL		   = 0x%1x\n",tr->MR_WL 	  ));
-	mcSHOW_DBG_MSG(("MR_RL		   = 0x%1x\n",tr->MR_RL 	  ));
-	mcSHOW_DBG_MSG(("BL 		   = 0x%1x\n",tr->BL		  ));
-	mcSHOW_DBG_MSG(("CK_Mode	   = 0x%1x\n",tr->CK_Mode	  ));
-	mcSHOW_DBG_MSG(("RPST		   = 0x%1x\n",tr->RPST		  ));
-	mcSHOW_DBG_MSG(("RD_PRE 	   = 0x%1x\n",tr->RD_PRE	  ));
-	mcSHOW_DBG_MSG(("RDQS_PRE	   = 0x%1x\n",tr->RDQS_PRE	  ));
-	mcSHOW_DBG_MSG(("WR_PRE 	   = 0x%1x\n",tr->WR_PRE	  ));
-	mcSHOW_DBG_MSG(("WR_PST 	   = 0x%1x\n",tr->WR_PST	  ));
-	mcSHOW_DBG_MSG(("DBI_WR 	   = 0x%1x\n",tr->DBI_WR	  ));
-	mcSHOW_DBG_MSG(("DBI_RD 	   = 0x%1x\n",tr->DBI_RD	  ));
-	mcSHOW_DBG_MSG(("DMI		   = 0x%1x\n",tr->DMI		  ));
-	mcSHOW_DBG_MSG(("OTF		   = 0x%1x\n",tr->OTF		  ));
-	mcSHOW_DBG_MSG(("WCK_PST	   = 0x%1x\n",tr->WCK_PST	  ));
-	mcSHOW_DBG_MSG(("RDQS_PST	   = 0x%1x\n",tr->RDQS_PST	  ));
-	mcSHOW_DBG_MSG(("CA_ODT 	   = 0x%1x\n",tr->CA_ODT	  ));
-	mcSHOW_DBG_MSG(("DQ_ODT 	   = 0x%1x\n",tr->DQ_ODT	  ));
-	mcSHOW_DBG_MSG(("CKR		   = 0x%1x\n",tr->CKR		  ));
-	mcSHOW_DBG_MSG(("WCK_ON 	   = 0x%1x\n",tr->WCK_ON	  ));
-	mcSHOW_DBG_MSG(("WCK_FM 	   = 0x%1x\n",tr->WCK_FM	  ));
-	mcSHOW_DBG_MSG(("WCK_ODT	   = 0x%1x\n",tr->WCK_ODT	  ));
-	mcSHOW_DBG_MSG(("DVFSQ		   = 0x%1x\n",tr->DVFSQ 	  ));
-	mcSHOW_DBG_MSG(("DVFSC		   = 0x%1x\n",tr->DVFSC 	  ));
-	mcSHOW_DBG_MSG(("RDQSmode[0]   = 0x%1x\n",tr->RDQSmode[0] ));
-	mcSHOW_DBG_MSG(("RDQSmode[1]   = 0x%1x\n",tr->RDQSmode[1] ));
-	mcSHOW_DBG_MSG(("WCKmode[0]    = 0x%1x\n",tr->WCKmode[0]  ));
-	mcSHOW_DBG_MSG(("WCKmode[1]    = 0x%1x\n",tr->WCKmode[1]  ));
-	mcSHOW_DBG_MSG(("RECC		   = 0x%1x\n",tr->RECC		  ));
-	mcSHOW_DBG_MSG(("WECC		   = 0x%1x\n",tr->WECC		  ));
-	mcSHOW_DBG_MSG(("BankMode	   = 0x%1x\n",tr->BankMode	  ));
-	mcSHOW_DBG_MSG(("WORK_FSP	   = 0x%1x\n",tr->WORK_FSP	  ));
-	mcSHOW_DBG_MSG(("=================================== \n"));
+	msg("=================================== \n");
+	msg("LPDDR5 DRAM CONFIGURATION\n"	  );
+	msg("=================================== \n");
+	msg("MR_WL		   = 0x%1x\n",tr->MR_WL 	  );
+	msg("MR_RL		   = 0x%1x\n",tr->MR_RL 	  );
+	msg("BL 		   = 0x%1x\n",tr->BL		  );
+	msg("CK_Mode	   = 0x%1x\n",tr->CK_Mode	  );
+	msg("RPST		   = 0x%1x\n",tr->RPST		  );
+	msg("RD_PRE 	   = 0x%1x\n",tr->RD_PRE	  );
+	msg("RDQS_PRE	   = 0x%1x\n",tr->RDQS_PRE	  );
+	msg("WR_PRE 	   = 0x%1x\n",tr->WR_PRE	  );
+	msg("WR_PST 	   = 0x%1x\n",tr->WR_PST	  );
+	msg("DBI_WR 	   = 0x%1x\n",tr->DBI_WR	  );
+	msg("DBI_RD 	   = 0x%1x\n",tr->DBI_RD	  );
+	msg("DMI		   = 0x%1x\n",tr->DMI		  );
+	msg("OTF		   = 0x%1x\n",tr->OTF		  );
+	msg("WCK_PST	   = 0x%1x\n",tr->WCK_PST	  );
+	msg("RDQS_PST	   = 0x%1x\n",tr->RDQS_PST	  );
+	msg("CA_ODT 	   = 0x%1x\n",tr->CA_ODT	  );
+	msg("DQ_ODT 	   = 0x%1x\n",tr->DQ_ODT	  );
+	msg("CKR		   = 0x%1x\n",tr->CKR		  );
+	msg("WCK_ON 	   = 0x%1x\n",tr->WCK_ON	  );
+	msg("WCK_FM 	   = 0x%1x\n",tr->WCK_FM	  );
+	msg("WCK_ODT	   = 0x%1x\n",tr->WCK_ODT	  );
+	msg("DVFSQ		   = 0x%1x\n",tr->DVFSQ 	  );
+	msg("DVFSC		   = 0x%1x\n",tr->DVFSC 	  );
+	msg("RDQSmode[0]   = 0x%1x\n",tr->RDQSmode[0] );
+	msg("RDQSmode[1]   = 0x%1x\n",tr->RDQSmode[1] );
+	msg("WCKmode[0]    = 0x%1x\n",tr->WCKmode[0]  );
+	msg("WCKmode[1]    = 0x%1x\n",tr->WCKmode[1]  );
+	msg("RECC		   = 0x%1x\n",tr->RECC		  );
+	msg("WECC		   = 0x%1x\n",tr->WECC		  );
+	msg("BankMode	   = 0x%1x\n",tr->BankMode	  );
+	msg("WORK_FSP	   = 0x%1x\n",tr->WORK_FSP	  );
+	msg("=================================== \n");
 }
diff --git a/src/vendorcode/mediatek/mt8192/dramc/Hal_io.c b/src/vendorcode/mediatek/mt8192/dramc/Hal_io.c
index d0f7c769a4..cab57d6d0f 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/Hal_io.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/Hal_io.c
@@ -254,7 +254,7 @@ inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value)
 #ifdef DUMP_INIT_RG_LOG_TO_DE
 	if (gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag == 1)
 	{
-		mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",u4reg_addr,u4reg_value));
+		mcSHOW_DUMP_INIT_RG_MSG("*(UINT32P)(0x%x) = 0x%x;\n",u4reg_addr,u4reg_value);
 		gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 0;
 		mcDELAY_MS(1); // to receive log for log
 		gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1;
@@ -264,7 +264,7 @@ inline void _ucDram_Register_Write(U64 u4reg_addr, U32 u4reg_value)
 #if REG_ACCESS_PORTING_DGB
 	if (RegLogEnable)
 	{
-		mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG]   ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value));
+		msg("\n[REG_ACCESS_PORTING_DBG]   ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value);
 	}
 #endif
 }
@@ -276,7 +276,7 @@ void ucDram_Register_Write(DRAMC_CTX_T *p, U32 u4reg_addr, U32 u4reg_value)
 	//CheckDramcWBR(u4reg_addr);
 #endif
 
-	//mcSHOW_DBG_MSG(("\n[REG_ACCESS_PORTING_DBG]	ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value));
+	//msg("\n[REG_ACCESS_PORTING_DBG]	ucDramC_Register_Write Reg(0x%X) = 0x%X\n", u4reg_addr, u4reg_value);
 	u4reg_addr = u4RegBaseAddrTraslate(p->ShuRGAccessIdx, p->rank, u4reg_addr);
 
 	_ucDram_Register_Write(u4reg_addr, u4reg_value);
@@ -304,7 +304,7 @@ U32 u4RegType = (reg32 & (0x1f << POS_BANK_NUM));
 #if __ETT__
 	if (GetDramcBroadcast()==DRAMC_BROADCAST_ON)
 	{
-		mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32));
+		err("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32);
 		while (1);
 	}
 #endif
@@ -351,7 +351,7 @@ void vIO32Write4BMsk_All2(DRAMC_CTX_T *p, U32 reg32, U32 val32, U32 msk32)
 #if __ETT__
 	if (GetDramcBroadcast()==DRAMC_BROADCAST_ON)
 	{
-		mcSHOW_ERR_MSG(("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32));
+		err("Error! virtual address 0x%x don't have to use write_all when Dramc WBR is on\n", reg32);
 		while (1);
 	}
 #endif
diff --git a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c
index bb7f0acea5..53fdb16873 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/LP4_dram_init.c
@@ -8,7 +8,7 @@ void CKE_FIX_ON(DRAMC_CTX_T *p, U8 EN, U8 rank)
 	{
 		case 0 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKEFIXON));  break;
 		case 1 : vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), P_Fld(EN, CKECTRL_CKE1FIXON)); break;
-		default: mcSHOW_DBG_MSG(("ERROR: CKE FIX ON error. Unexpected Rank	\n"));
+		default: msg("ERROR: CKE FIX ON error. Unexpected Rank	\n");
 	}
 }
 //[SV] task LP4_MRS(bit [7:0] reg_addr, bit[7:0] reg_op, bit[1:0] rank);
@@ -16,7 +16,7 @@ static void LP4_MRS(DRAMC_CTX_T *p, U16 reg_addr, U8 reg_op, U8 rank)
 {
 	U8 temp_MRS_RESPONSE  ;
 
-	mcSHOW_DBG_MSG(("[LP4_DRAM_INIT_MRS] RK:%1d-MA:%2d-OP:0x%2x @Channle:%1d\n",rank,reg_addr,reg_op,vGetPHY2ChannelMapping(p)));
+	msg("[LP4_DRAM_INIT_MRS] RK:%1d-MA:%2d-OP:0x%2x @Channle:%1d\n",rank,reg_addr,reg_op,vGetPHY2ChannelMapping(p));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_CTRL0), P_Fld(rank , SWCMD_CTRL0_MRSRK	   ) \
 															| P_Fld(reg_addr, SWCMD_CTRL0_MRSMA    ) \
 															| P_Fld(reg_op	, SWCMD_CTRL0_MRSOP    ));
@@ -91,7 +91,7 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra
 	DramcZQCalibration(p, rank); //ZQ calobration should be done before CBT calibration by switching to low frequency
 	#endif
 
-	mcSHOW_DBG_MSG(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d >>>>>>\n",vGetPHY2ChannelMapping(p),rank));
+	msg("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d >>>>>>\n",vGetPHY2ChannelMapping(p),rank);
 
 	//first FSP
 	if(tr->WORK_FSP == 0) {LP4_FSP_WR_or_OP(p, 0, 1, rank);}
@@ -130,12 +130,12 @@ static void lp4_dram_init_single_rank(DRAMC_CTX_T *p,LP4_DRAM_CONFIG_T *tr,U8 ra
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7)	  , P_Fld( 1	   , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y	 ));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7)	  , P_Fld( 1	   , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y	 ));
 
-	mcSHOW_DBG_MSG(("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d <<<<<<\n",vGetPHY2ChannelMapping(p),rank));
+	msg("[LP4_DRAM_INIT] Channle:%1d-Rank:%1d <<<<<<\n",vGetPHY2ChannelMapping(p),rank);
 }
 
 void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN)
 {
-	mcSHOW_DBG_MSG(("============ LP4 DIFF to SE enter ============\n"));
+	msg("============ LP4 DIFF to SE enter ============\n");
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD13), P_Fld( LP4Y_EN , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA ) \
 															  | P_Fld( LP4Y_EN		 , SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA  ));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ13) , P_Fld( LP4Y_EN , SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0  ) \
@@ -160,7 +160,7 @@ void LP4_single_end_DRAMC_post_config(DRAMC_CTX_T *p, U8 LP4Y_EN)
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B0_DQ7)	  , P_Fld( 1 , B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0_LP4Y    ));
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_B1_DQ7)	  , P_Fld( 1 , B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1_LP4Y    ));
 #endif
-	mcSHOW_DBG_MSG(("============ LP4 DIFF to SE exit  ============\n"));
+	msg("============ LP4 DIFF to SE exit  ============\n");
 }
 
 void LP4_DRAM_INIT(DRAMC_CTX_T *p)
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c
index a4f1b2f285..529ef5906f 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_actiming.c
@@ -51,8 +51,8 @@ static U8 u1GetACTimingIdx(DRAMC_CTX_T *p)
 			   )
 			{
 				u1TimingIdx = u1TmpIdx;
-				mcSHOW_DBG_MSG(("match AC timing %d\n", u1TimingIdx));
-				mcDUMP_REG_MSG(("match AC timing %d\n", u1TimingIdx));
+				msg("match AC timing %d\n", u1TimingIdx);
+				reg_msg("match AC timing %d\n", u1TimingIdx);
 				break;
 			}
 		}
@@ -71,9 +71,9 @@ static U8 u1GetACTimingIdx(DRAMC_CTX_T *p)
 			   )
 			{
 				u1TimingIdx = u1TmpIdx;
-				mcSHOW_DBG_MSG(("match AC timing %d\n", u1TimingIdx));
-				mcDUMP_REG_MSG(("match AC timing %d\n", u1TimingIdx));
-				mcSHOW_DBG_MSG(("dramType %d, freq %d, readDBI %d, DivMode %d, cbtMode %d\n", u1TmpDramType, p->freqGroup, p->DBI_R_onoff[p->dram_fsp], vGet_Div_Mode(p), vGet_Dram_CBT_Mode(p)));
+				msg("match AC timing %d\n", u1TimingIdx);
+				reg_msg("match AC timing %d\n", u1TimingIdx);
+				msg("dramType %d, freq %d, readDBI %d, DivMode %d, cbtMode %d\n", u1TmpDramType, p->freqGroup, p->DBI_R_onoff[p->dram_fsp], vGet_Div_Mode(p), vGet_Dram_CBT_Mode(p));
 				break;
 			}
 		}
@@ -376,7 +376,7 @@ else
 	}
 	else
 	{
-		mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n"));
+		err("u4RankINCTL_ROOT <2, Please check\n");
 		u4RankINCTL_ROOT = 0;
 	}
 
@@ -480,7 +480,7 @@ static void WDQSMode2AcTimingEnlarge(DRAMC_CTX_T *p, U16 *u2_XRTW2W, U16 *u2_XRT
 			u2XRTR2W_enlarge = 1;
 			break;
 		default:
-			mcSHOW_ERR_MSG(("[WDQSMode2AcTimingEnlarge] frequency err!\n"));
+			err("[WDQSMode2AcTimingEnlarge] frequency err!\n");
 			#if __ETT__
 			while (1);
 			#endif
@@ -782,7 +782,7 @@ else
 	}
 	else
 	{
-		mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n"));
+		err("u4RankINCTL_ROOT <2, Please check\n");
 		u4RankINCTL_ROOT = 0;
 	}
 
@@ -847,7 +847,7 @@ DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p)
 {
 	U8 u1TimingIdx = 0;
 
-	mcSHOW_DBG_MSG3(("[UpdateACTiming]\n"));
+	msg3("[UpdateACTiming]\n");
 
 	//Retrieve ACTimingTable's corresponding index
 	u1TimingIdx = u1GetACTimingIdx(p);
@@ -859,9 +859,9 @@ DRAM_STATUS_T DdrUpdateACTiming(DRAMC_CTX_T *p)
 			u1TimingIdx = 0;
 		else // LPDDR3
 			u1TimingIdx = 6;
-		mcSHOW_ERR_MSG(("Error, no match AC timing, use default timing %d\n", u1TimingIdx));
+		err("Error, no match AC timing, use default timing %d\n", u1TimingIdx);
 		#else
-		mcSHOW_ERR_MSG(("Error, no match AC timing, not apply table\n"));
+		err("Error, no match AC timing, not apply table\n");
 		return DRAM_FAIL;
 		#endif
 	}
@@ -889,7 +889,7 @@ DRAM_STATUS_T DdrUpdateACTiming_EMI(DRAMC_CTX_T *p, AC_TIMING_EXTERNAL_T *ACRegF
 	ACTime_T_LP5 ACTime_LP5;
 	#endif
 	ACTime_T_LP4 ACTime_LP4;
-	mcSHOW_DBG_MSG3(("[DdrUpdateACTiming_EMI]\n"));
+	msg3("[DdrUpdateACTiming_EMI]\n");
 
    if (ACRegFromEmi == NULL)
 		return DRAM_FAIL;
@@ -1083,12 +1083,12 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p)
 	};
 
 
-	mcSHOW_DBG_MSG(("[ACTimingOptimize]"));
+	msg("[ACTimingOptimize]");
 
 #if __ETT__
 	if (p->density==0xff)
 	{
-		mcSHOW_ERR_MSG(("Error : No call MR8 to get density!!\n"));
+		err("Error : No call MR8 to get density!!\n");
 		while(1);
 	}
 #endif
@@ -1113,7 +1113,7 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p)
 			break;
 		default:
 			u1ExecuteOptimize = DISABLE;
-			mcSHOW_ERR_MSG(("MR8 density err!\n"));
+			err("MR8 density err!\n");
 	}
 	/* Set freqGroup Idx */
 	switch (p->freqGroup)
@@ -1124,7 +1124,7 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p)
 			else
 			{
 				u1ExecuteOptimize = DISABLE;
-				mcSHOW_ERR_MSG(("freqGroup err!\n"));
+				err("freqGroup err!\n");
 				#if __ETT__
 				while(1);
 				#endif
@@ -1162,7 +1162,7 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p)
 			break;
 		default:
 			u1ExecuteOptimize = DISABLE;
-			mcSHOW_ERR_MSG(("freqGroup err!\n"));
+			err("freqGroup err!\n");
 			#if __ETT__
 			while(1);
 			#endif
@@ -1171,7 +1171,7 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p)
 	if (vGet_Div_Mode(p) == DIV4_MODE && u1FreqGrpIdx >= GRP_ACTIM_NUM_DIV4)
 	{
 			u1ExecuteOptimize = DISABLE;
-			mcSHOW_ERR_MSG(("freqGroup err!\n"));
+			err("freqGroup err!\n");
 			#if __ETT__
 			while(1);
 			#endif
@@ -1196,7 +1196,7 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p)
 		vIO32WriteFldAlign_All(DRAMC_REG_SHU_ACTIM3, u1TRFCpb, SHU_ACTIM3_TRFCPB);
 		vIO32WriteFldAlign_All(DRAMC_REG_SHU_AC_TIME_05T, u1TRFCpb_05T, SHU_AC_TIME_05T_TRFCPB_05T);
 
-		mcSHOW_DBG_MSG(("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, TRFCpb %u, TRFCpb_05T %u\n", p->density, u1TRFC, u1TRFC_05T, u1TXREFCNT, u1TRFCpb, u1TRFCpb_05T));
+		msg("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, TRFCpb %u, TRFCpb_05T %u\n", p->density, u1TRFC, u1TRFC_05T, u1TXREFCNT, u1TRFCpb, u1TRFCpb_05T);
 	}
 
 	return;
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c
index f053ec4690..e16b7e9400 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_dv_freq_related.c
@@ -32,16 +32,16 @@ void CInit_ConfigFromTBA(void)
 	TbaConfig.DBI_R_onoff_FSP1	= 0;
 	TbaConfig.frequency 		= 1600;
 	TbaConfig.voltage_state 	= 3;
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dramc_dram_ratio  = %1d\n", TbaConfig.dramc_dram_ratio));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: channel		   = %1d\n", TbaConfig.channel));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_type		   = %1d\n", TbaConfig.dram_type));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: shu_type		   = %1d\n", TbaConfig.shu_type));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_cbt_mode_RK0 = %1d\n", TbaConfig.dram_cbt_mode_RK0));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: dram_cbt_mode_RK1 = %1d\n", TbaConfig.dram_cbt_mode_RK1));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: DBI_R_onoff_FSP0  = %1d\n", TbaConfig.DBI_R_onoff_FSP0));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: DBI_R_onoff_FSP1  = %1d\n", TbaConfig.DBI_R_onoff_FSP1));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: frequency		   = %1d\n", TbaConfig.frequency));
-	mcSHOW_DBG_MSG(("[TBA_CTX_T] Global: voltage_state	   = %1d\n", TbaConfig.voltage_state));
+	msg("[TBA_CTX_T] Global: dramc_dram_ratio  = %1d\n", TbaConfig.dramc_dram_ratio);
+	msg("[TBA_CTX_T] Global: channel		   = %1d\n", TbaConfig.channel);
+	msg("[TBA_CTX_T] Global: dram_type		   = %1d\n", TbaConfig.dram_type);
+	msg("[TBA_CTX_T] Global: shu_type		   = %1d\n", TbaConfig.shu_type);
+	msg("[TBA_CTX_T] Global: dram_cbt_mode_RK0 = %1d\n", TbaConfig.dram_cbt_mode_RK0);
+	msg("[TBA_CTX_T] Global: dram_cbt_mode_RK1 = %1d\n", TbaConfig.dram_cbt_mode_RK1);
+	msg("[TBA_CTX_T] Global: DBI_R_onoff_FSP0  = %1d\n", TbaConfig.DBI_R_onoff_FSP0);
+	msg("[TBA_CTX_T] Global: DBI_R_onoff_FSP1  = %1d\n", TbaConfig.DBI_R_onoff_FSP1);
+	msg("[TBA_CTX_T] Global: frequency		   = %1d\n", TbaConfig.frequency);
+	msg("[TBA_CTX_T] Global: voltage_state	   = %1d\n", TbaConfig.voltage_state);
 
 
 	TbaEnvConfig.TMRRI_way			   = 1;
@@ -62,27 +62,27 @@ void CInit_ConfigFromTBA(void)
 	TbaEnvConfig.WPST1P5T_OPT		   = 1;
 	TbaEnvConfig.TXP_WORKAROUND_OPT    = 0;
 	TbaEnvConfig.DLL_IDLE_MODE		   = 1;
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TMRRI_way 			= %1d\n", TbaEnvConfig.TMRRI_way));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RUNTIMEMRR_way		= %1d\n", TbaEnvConfig.RUNTIMEMRR_way));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: PICG_MODE 			= %1d\n", TbaEnvConfig.PICG_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: LP_NEW8X_SEQ_MODE 	= %1d\n", TbaEnvConfig.LP_NEW8X_SEQ_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: DDR400_OPEN_LOOP_MODE = %1d\n", TbaEnvConfig.DDR400_OPEN_LOOP_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RXTRACK_PBYTE_OPT 	= %1d\n", TbaEnvConfig.RXTRACK_PBYTE_OPT));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: RG_SPM_MODE			= %1d\n", TbaEnvConfig.RG_SPM_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TX_OE_EXT_OPT 		= %1d\n", TbaEnvConfig.TX_OE_EXT_OPT));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: PLL_MODE_OPTION		= %1d\n", TbaEnvConfig.PLL_MODE_OPTION));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TREFBWIG_IGNORE		= %1d\n", TbaEnvConfig.TREFBWIG_IGNORE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: SHUFFLE_LVL_MODE		= %1d\n", TbaEnvConfig.SHUFFLE_LVL_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: SELPH_MODE			= %1d\n", TbaEnvConfig.SELPH_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TRACK_UP_MODE 		= %1d\n", TbaEnvConfig.TRACK_UP_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: VALID_LAT_VALUE		= %1d\n", TbaEnvConfig.VALID_LAT_VALUE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: NEW_RANK_MODE 		= %1d\n", TbaEnvConfig.NEW_RANK_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: WPST1P5T_OPT			= %1d\n", TbaEnvConfig.WPST1P5T_OPT));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: TXP_WORKAROUND_OPT	= %1d\n", TbaEnvConfig.TXP_WORKAROUND_OPT));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_config_T] Global: DLL_IDLE_MODE 		= %1d\n", TbaEnvConfig.DLL_IDLE_MODE));
+	msg("[TBA_dramc_env_config_T] Global: TMRRI_way 			= %1d\n", TbaEnvConfig.TMRRI_way);
+	msg("[TBA_dramc_env_config_T] Global: RUNTIMEMRR_way		= %1d\n", TbaEnvConfig.RUNTIMEMRR_way);
+	msg("[TBA_dramc_env_config_T] Global: PICG_MODE 			= %1d\n", TbaEnvConfig.PICG_MODE);
+	msg("[TBA_dramc_env_config_T] Global: LP_NEW8X_SEQ_MODE 	= %1d\n", TbaEnvConfig.LP_NEW8X_SEQ_MODE);
+	msg("[TBA_dramc_env_config_T] Global: DDR400_OPEN_LOOP_MODE = %1d\n", TbaEnvConfig.DDR400_OPEN_LOOP_MODE);
+	msg("[TBA_dramc_env_config_T] Global: RXTRACK_PBYTE_OPT 	= %1d\n", TbaEnvConfig.RXTRACK_PBYTE_OPT);
+	msg("[TBA_dramc_env_config_T] Global: RG_SPM_MODE			= %1d\n", TbaEnvConfig.RG_SPM_MODE);
+	msg("[TBA_dramc_env_config_T] Global: TX_OE_EXT_OPT 		= %1d\n", TbaEnvConfig.TX_OE_EXT_OPT);
+	msg("[TBA_dramc_env_config_T] Global: PLL_MODE_OPTION		= %1d\n", TbaEnvConfig.PLL_MODE_OPTION);
+	msg("[TBA_dramc_env_config_T] Global: TREFBWIG_IGNORE		= %1d\n", TbaEnvConfig.TREFBWIG_IGNORE);
+	msg("[TBA_dramc_env_config_T] Global: SHUFFLE_LVL_MODE		= %1d\n", TbaEnvConfig.SHUFFLE_LVL_MODE);
+	msg("[TBA_dramc_env_config_T] Global: SELPH_MODE			= %1d\n", TbaEnvConfig.SELPH_MODE);
+	msg("[TBA_dramc_env_config_T] Global: TRACK_UP_MODE 		= %1d\n", TbaEnvConfig.TRACK_UP_MODE);
+	msg("[TBA_dramc_env_config_T] Global: VALID_LAT_VALUE		= %1d\n", TbaEnvConfig.VALID_LAT_VALUE);
+	msg("[TBA_dramc_env_config_T] Global: NEW_RANK_MODE 		= %1d\n", TbaEnvConfig.NEW_RANK_MODE);
+	msg("[TBA_dramc_env_config_T] Global: WPST1P5T_OPT			= %1d\n", TbaEnvConfig.WPST1P5T_OPT);
+	msg("[TBA_dramc_env_config_T] Global: TXP_WORKAROUND_OPT	= %1d\n", TbaEnvConfig.TXP_WORKAROUND_OPT);
+	msg("[TBA_dramc_env_config_T] Global: DLL_IDLE_MODE 		= %1d\n", TbaEnvConfig.DLL_IDLE_MODE);
 
 	TBA_Build_Def.DQSG_TRACK_on = 1;
-	mcSHOW_DBG_MSG(("[TBA_build_def_T] Global: DQSG_TRACK_on = %1d\n", TBA_Build_Def.DQSG_TRACK_on));
+	msg("[TBA_build_def_T] Global: DQSG_TRACK_on = %1d\n", TBA_Build_Def.DQSG_TRACK_on);
 
 
 	TbaEnvDVFSCfg.group_num 			= 2;
@@ -93,14 +93,14 @@ void CInit_ConfigFromTBA(void)
 	TbaEnvDVFSCfg.DQSIEN_MODE			= 1;
 	TbaEnvDVFSCfg.freq_group_map_0		= 2;
 	TbaEnvDVFSCfg.freq_group_map_1		= 6;
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: group_num		= %1d\n", TbaEnvDVFSCfg.group_num));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5BGOTF 		= %1d\n", TbaEnvDVFSCfg.LP5BGOTF));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5BGEN			= %1d\n", TbaEnvDVFSCfg.LP5BGEN));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: CAS_MODE 		= %1d\n", TbaEnvDVFSCfg.CAS_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: LP5_RDQS_SE_EN	= %1d\n", TbaEnvDVFSCfg.LP5_RDQS_SE_EN));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: DQSIEN_MODE		= %1d\n", TbaEnvDVFSCfg.DQSIEN_MODE));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: freq_group_map_0 = %1d\n", TbaEnvDVFSCfg.freq_group_map_0));
-	mcSHOW_DBG_MSG(("[TBA_dramc_env_dvfs_config_T] Global: freq_group_map_1 = %1d\n", TbaEnvDVFSCfg.freq_group_map_1));
+	msg("[TBA_dramc_env_dvfs_config_T] Global: group_num		= %1d\n", TbaEnvDVFSCfg.group_num);
+	msg("[TBA_dramc_env_dvfs_config_T] Global: LP5BGOTF 		= %1d\n", TbaEnvDVFSCfg.LP5BGOTF);
+	msg("[TBA_dramc_env_dvfs_config_T] Global: LP5BGEN			= %1d\n", TbaEnvDVFSCfg.LP5BGEN);
+	msg("[TBA_dramc_env_dvfs_config_T] Global: CAS_MODE 		= %1d\n", TbaEnvDVFSCfg.CAS_MODE);
+	msg("[TBA_dramc_env_dvfs_config_T] Global: LP5_RDQS_SE_EN	= %1d\n", TbaEnvDVFSCfg.LP5_RDQS_SE_EN);
+	msg("[TBA_dramc_env_dvfs_config_T] Global: DQSIEN_MODE		= %1d\n", TbaEnvDVFSCfg.DQSIEN_MODE);
+	msg("[TBA_dramc_env_dvfs_config_T] Global: freq_group_map_0 = %1d\n", TbaEnvDVFSCfg.freq_group_map_0);
+	msg("[TBA_dramc_env_dvfs_config_T] Global: freq_group_map_1 = %1d\n", TbaEnvDVFSCfg.freq_group_map_1);
 
 
 	TbaEnvHwFuncCfg.HW_MR4_OPTION_RANDOM			 = 1;
@@ -118,21 +118,21 @@ void CInit_ConfigFromTBA(void)
 	TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_EN			 = 1;
 	TbaEnvHwFuncCfg.RDSEL_TRACK_EN					 = 0;
 	TbaEnvHwFuncCfg.DQSG_TRACK_EN					 = 0;
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_MR4_OPTION_RANDOM			   = %1d\n", TbaEnvHwFuncCfg.HW_MR4_OPTION_RANDOM));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DMYRD_OPTION_RANDOM		   = %1d\n", TbaEnvHwFuncCfg.HW_DMYRD_OPTION_RANDOM));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DQSOSC_OPTION_RANDOM		   = %1d\n", TbaEnvHwFuncCfg.HW_DQSOSC_OPTION_RANDOM));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_ZQ_OPTION_RANDOM			   = %1d\n", TbaEnvHwFuncCfg.HW_ZQ_OPTION_RANDOM));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RX_INPUT_TRACK_OPTION_RANDOM	   = %1d\n", TbaEnvHwFuncCfg.RX_INPUT_TRACK_OPTION_RANDOM));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RUNTIME_DEBUG_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_OPTION_RANDOM));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_MR4_EN 					   = %1d\n", TbaEnvHwFuncCfg.HW_MR4_EN));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DMYRD_EN					   = %1d\n", TbaEnvHwFuncCfg.HW_DMYRD_EN));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_DQSOSC_EN					   = %1d\n", TbaEnvHwFuncCfg.HW_DQSOSC_EN));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: HW_ZQ_EN						   = %1d\n", TbaEnvHwFuncCfg.HW_ZQ_EN));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RETRY_EN 				   = %1d\n", TbaEnvHwFuncCfg.DQSG_RETRY_EN));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RX_INPUT_TRACK_EN 			   = %1d\n", TbaEnvHwFuncCfg.RX_INPUT_TRACK_EN));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_RUNTIME_DEBUG_EN 		   = %1d\n", TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_EN));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: RDSEL_TRACK_EN				   = %1d\n", TbaEnvHwFuncCfg.RDSEL_TRACK_EN));
-	mcSHOW_DBG_MSG(("[dramc_env_hw_func_config_T] Global: DQSG_TRACK_EN 				   = %1d\n", TbaEnvHwFuncCfg.DQSG_TRACK_EN));
+	msg("[dramc_env_hw_func_config_T] Global: HW_MR4_OPTION_RANDOM			   = %1d\n", TbaEnvHwFuncCfg.HW_MR4_OPTION_RANDOM);
+	msg("[dramc_env_hw_func_config_T] Global: HW_DMYRD_OPTION_RANDOM		   = %1d\n", TbaEnvHwFuncCfg.HW_DMYRD_OPTION_RANDOM);
+	msg("[dramc_env_hw_func_config_T] Global: HW_DQSOSC_OPTION_RANDOM		   = %1d\n", TbaEnvHwFuncCfg.HW_DQSOSC_OPTION_RANDOM);
+	msg("[dramc_env_hw_func_config_T] Global: HW_ZQ_OPTION_RANDOM			   = %1d\n", TbaEnvHwFuncCfg.HW_ZQ_OPTION_RANDOM);
+	msg("[dramc_env_hw_func_config_T] Global: RX_INPUT_TRACK_OPTION_RANDOM	   = %1d\n", TbaEnvHwFuncCfg.RX_INPUT_TRACK_OPTION_RANDOM);
+	msg("[dramc_env_hw_func_config_T] Global: DQSG_RUNTIME_DEBUG_OPTION_RANDOM = %1d\n", TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_OPTION_RANDOM);
+	msg("[dramc_env_hw_func_config_T] Global: HW_MR4_EN 					   = %1d\n", TbaEnvHwFuncCfg.HW_MR4_EN);
+	msg("[dramc_env_hw_func_config_T] Global: HW_DMYRD_EN					   = %1d\n", TbaEnvHwFuncCfg.HW_DMYRD_EN);
+	msg("[dramc_env_hw_func_config_T] Global: HW_DQSOSC_EN					   = %1d\n", TbaEnvHwFuncCfg.HW_DQSOSC_EN);
+	msg("[dramc_env_hw_func_config_T] Global: HW_ZQ_EN						   = %1d\n", TbaEnvHwFuncCfg.HW_ZQ_EN);
+	msg("[dramc_env_hw_func_config_T] Global: DQSG_RETRY_EN 				   = %1d\n", TbaEnvHwFuncCfg.DQSG_RETRY_EN);
+	msg("[dramc_env_hw_func_config_T] Global: RX_INPUT_TRACK_EN 			   = %1d\n", TbaEnvHwFuncCfg.RX_INPUT_TRACK_EN);
+	msg("[dramc_env_hw_func_config_T] Global: DQSG_RUNTIME_DEBUG_EN 		   = %1d\n", TbaEnvHwFuncCfg.DQSG_RUNTIME_DEBUG_EN);
+	msg("[dramc_env_hw_func_config_T] Global: RDSEL_TRACK_EN				   = %1d\n", TbaEnvHwFuncCfg.RDSEL_TRACK_EN);
+	msg("[dramc_env_hw_func_config_T] Global: DQSG_TRACK_EN 				   = %1d\n", TbaEnvHwFuncCfg.DQSG_TRACK_EN);
 
 
 	TbaTestListDef.RandDefaultData_on	   = 1;
@@ -145,15 +145,15 @@ void CInit_ConfigFromTBA(void)
 	TbaTestListDef.LP45_COMBO_APHY_EN	   = 1;
 	TbaTestListDef.LPDDR5_EN			   = 0;
 	TbaTestListDef.LP3_4_PINMUX_EN		   = 0;
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: RandDefaultData_on	  = %1d\n", TbaTestListDef.RandDefaultData_on));
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: DQS2DQ_TRACK_on		  = %1d\n", TbaTestListDef.DQS2DQ_TRACK_on));
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LPDDR4_EN 			  = %1d\n", TbaTestListDef.LPDDR4_EN));
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: ESL_LOG_GEN			  = %1d\n", TbaTestListDef.ESL_LOG_GEN));
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP4_X8_on 			  = %1d\n", TbaTestListDef.LP4_X8_on));
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: INCLUDE_LP45_COMBO_APHY = %1d\n", TbaTestListDef.INCLUDE_LP45_COMBO_APHY));
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP45_COMBO_APHY_EN	  = %1d\n", TbaTestListDef.LP45_COMBO_APHY_EN));
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LPDDR5_EN 			  = %1d\n", TbaTestListDef.LPDDR5_EN));
-	mcSHOW_DBG_MSG(("[TBA_TestList_Def_T] Global: LP3_4_PINMUX_EN		  = %1d\n", TbaTestListDef.LP3_4_PINMUX_EN));
+	msg("[TBA_TestList_Def_T] Global: RandDefaultData_on	  = %1d\n", TbaTestListDef.RandDefaultData_on);
+	msg("[TBA_TestList_Def_T] Global: DQS2DQ_TRACK_on		  = %1d\n", TbaTestListDef.DQS2DQ_TRACK_on);
+	msg("[TBA_TestList_Def_T] Global: LPDDR4_EN 			  = %1d\n", TbaTestListDef.LPDDR4_EN);
+	msg("[TBA_TestList_Def_T] Global: ESL_LOG_GEN			  = %1d\n", TbaTestListDef.ESL_LOG_GEN);
+	msg("[TBA_TestList_Def_T] Global: LP4_X8_on 			  = %1d\n", TbaTestListDef.LP4_X8_on);
+	msg("[TBA_TestList_Def_T] Global: INCLUDE_LP45_COMBO_APHY = %1d\n", TbaTestListDef.INCLUDE_LP45_COMBO_APHY);
+	msg("[TBA_TestList_Def_T] Global: LP45_COMBO_APHY_EN	  = %1d\n", TbaTestListDef.LP45_COMBO_APHY_EN);
+	msg("[TBA_TestList_Def_T] Global: LPDDR5_EN 			  = %1d\n", TbaTestListDef.LPDDR5_EN);
+	msg("[TBA_TestList_Def_T] Global: LP3_4_PINMUX_EN		  = %1d\n", TbaTestListDef.LP3_4_PINMUX_EN);
 
 
 
@@ -197,45 +197,45 @@ void CInit_ConfigFromTBA(void)
 	TbaDramcBenchConfig.chb_pinmux_anti_order_14 = 14;
 	TbaDramcBenchConfig.chb_pinmux_anti_order_15 = 15;
 
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: rank_swap				  = %1d\n", TbaDramcBenchConfig.rank_swap));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: new_uP_spm_mode		  = %1d\n", TbaDramcBenchConfig.new_uP_spm_mode));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: LP_MTCMOS_CONTROL_SEL	  = %1d\n", TbaDramcBenchConfig.LP_MTCMOS_CONTROL_SEL));
+	msg("[TBA_dramc_bench_T] Global: rank_swap				  = %1d\n", TbaDramcBenchConfig.rank_swap);
+	msg("[TBA_dramc_bench_T] Global: new_uP_spm_mode		  = %1d\n", TbaDramcBenchConfig.new_uP_spm_mode);
+	msg("[TBA_dramc_bench_T] Global: LP_MTCMOS_CONTROL_SEL	  = %1d\n", TbaDramcBenchConfig.LP_MTCMOS_CONTROL_SEL);
 	// CHA, BYTE 0
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_0  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_0));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_1  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_1));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_2  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_2));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_3  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_3));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_4  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_4));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_5  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_5));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_6  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_6));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_7  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_7));
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_0  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_0);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_1  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_1);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_2  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_2);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_3  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_3);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_4  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_4);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_5  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_5);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_6  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_6);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_7  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_7);
 	// CHA BYTE 1
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_8  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_8));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_9  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_9));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_10));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_11 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_11));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_12 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_12));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_13));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_14));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_15));
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_8  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_8);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_9  = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_9);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_10);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_11 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_11);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_12 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_12);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_13);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_14);
+	msg("[TBA_dramc_bench_T] Global: cha_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.cha_pinmux_anti_order_15);
 	// CHB, BYTE 0
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_0  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_0));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_1  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_1));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_2  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_2));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_3  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_3));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_4  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_4));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_5  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_5));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_6  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_6));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_7  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_7));
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_0  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_0);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_1  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_1);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_2  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_2);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_3  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_3);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_4  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_4);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_5  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_5);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_6  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_6);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_7  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_7);
 	// CHB, BYTE 1
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_8  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_8));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_9  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_9));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_10));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_11 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_11));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_12 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_12));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_13));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_14));
-	mcSHOW_DBG_MSG(("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_15));
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_8  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_8);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_9  = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_9);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_10 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_10);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_11 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_11);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_12 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_12);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_13 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_13);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_14 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_14);
+	msg("[TBA_dramc_bench_T] Global: chb_pinmux_anti_order_15 = %1d\n", TbaDramcBenchConfig.chb_pinmux_anti_order_15);
 
 }
 #endif
@@ -391,8 +391,8 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)
 											P_Fld((U32)0x46, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
 											P_Fld((U32)0x46, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
 
-			//mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
-			//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+			//msg("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+			//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly);
 		}
 
 		{
@@ -656,8 +656,8 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)
 											P_Fld((U32)pRxB1DQ[u1BitIdx], SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
 											P_Fld((U32)pRxB1DQ[u1BitIdx+1], SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
 
-			//mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
-			//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+			//msg("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+			//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly);
 		}
 
 		{
@@ -903,8 +903,8 @@ void Apply_LP4_1600_Calibraton_Result(DRAMC_CTX_T *p)//simulation
 											P_Fld((U32)0x0, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
 											P_Fld((U32)0x0, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
 
-			//mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
-			//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+			//msg("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+			//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly);
 		}
 
 		{
@@ -1116,8 +1116,8 @@ void Apply_LP4_4266_Calibraton_Result(DRAMC_CTX_T *p)//simulation
 											P_Fld((U32)pRxB1DQ[u1BitIdx], SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
 											P_Fld((U32)pRxB1DQ[u1BitIdx+1], SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
 
-			//mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
-			//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+			//msg("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+			//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly);
 		}
 
 		{
@@ -8185,8 +8185,8 @@ void TX_Path_Algorithm(DRAMC_CTX_T *p)
 
 	//u1DQ_UI  = WL*DFS_TOP[0].CKR*2 - u1WDBI_EN*(DFS_TOP[0].DQ_P2S_RATIO) + (tDQSS+tDQS2DQ)*1000000/DFS_TOP[0].data_rate;
 
-	mcSHOW_DBG_MSG(("[TX_path_calculate] data rate=%d, WL=%d, DQS_TotalUI=%d\n", DFS_TOP[0].data_rate, WL, u1DQS_TotalUI));
-	mcSHOW_DBG_MSG(("[TX_path_calculate] DQS = (%d,%d) DQS_OE = (%d,%d)\n", u1DQS_MCK, u1DQS_UI, u1DQS_OE_MCK, u1DQS_OE_UI));
+	msg("[TX_path_calculate] data rate=%d, WL=%d, DQS_TotalUI=%d\n", DFS_TOP[0].data_rate, WL, u1DQS_TotalUI);
+	msg("[TX_path_calculate] DQS = (%d,%d) DQS_OE = (%d,%d)\n", u1DQS_MCK, u1DQS_UI, u1DQS_OE_MCK, u1DQS_OE_UI);
 
 	for(u1RandIdx = 0; u1RandIdx < p->support_rank_num; u1RandIdx ++)
 	{
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c
index fa01f516b0..7c74d4b293 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_dvfs.c
@@ -115,12 +115,12 @@ void FullRGDump(DRAMC_CTX_T *p, U8 step, U32 u4ShuOffset)
 {
 	U8 u1RankIdx=0;
 
-	mcSHOW_DBG_MSG(("[FullRGDump] STEP%d\n", step));
+	msg("[FullRGDump] STEP%d\n", step);
 	//Darren-DumpAoNonShuReg();
 	for (u1RankIdx=RANK_0; u1RankIdx<p->support_rank_num; u1RankIdx++)
 	{
 		vSetRank(p, u1RankIdx);
-		mcSHOW_DBG_MSG(("[FullRGDump] RANK%d\n", u1RankIdx));
+		msg("[FullRGDump] RANK%d\n", u1RankIdx);
 		DumpAoShuReg(u4ShuOffset, u4ShuOffset);
 	}
 	//Darren-DumpNaoReg();
@@ -156,7 +156,7 @@ U32 SramDebugModeRead(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg)
 	u4Value = u4IO32Read4B(DRAMC_REG_ADDR(u4Reg));// SHU1
 	DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
 	p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
-	mcSHOW_DBG_MSG(("[SramDebugModeRead] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Value));
+	msg("[SramDebugModeRead] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Value);
 
 	//vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
 	//vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x0, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
@@ -192,7 +192,7 @@ void SramDebugModeWrite(DRAMC_CTX_T *p, U8 sram_shu_level, U32 u4Reg, U32 u4Data
 	vIO32Write4B(DRAMC_REG_ADDR(u4Reg), u4Data); // SHU1
 	DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
 	p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
-	mcSHOW_DBG_MSG(("[SramDebugModeWrite] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Data));
+	msg("[SramDebugModeWrite] RK%d Reg=0x%x, Value=0x%x\n", p->rank, u4Reg, u4Data);
 
 	//vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA0, 0x0, MISC_SRAM_DMA0_APB_SLV_SEL);
 	//vIO32WriteFldAlign_All(DDRPHY_REG_MISC_SRAM_DMA1, 0x0, MISC_SRAM_DMA1_R_APB_DMA_DBG_ACCESS);
@@ -276,10 +276,10 @@ void DFSRuntimeMRW_preset(DRAMC_CTX_T *p, U8 sram_shu_level)
 		ch_end = CHANNEL_D;
 #endif
 
-	//Darren-mcSHOW_DBG_MSG(("[DFSRuntimeMRW_preset] FSP%d\n", p->dram_fsp));
+	//Darren-msg("[DFSRuntimeMRW_preset] FSP%d\n", p->dram_fsp);
 	//! save mr13
 	vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_15_0, u1MR13Value[RANK_0], LPIF_MR_OP_STORE_SHU_15_0_MR_OP_SET_SHU_15_0);
-	//Darren-mcSHOW_DBG_MSG(("\tMR13 = 0x%x\n", u1MR13Value[RANK_0]));
+	//Darren-msg("\tMR13 = 0x%x\n", u1MR13Value[RANK_0]);
 
 #if ENABLE_READ_DBI
 	u1MR03_Value = ((u1MR03Value[p->dram_fsp] & 0xbf) | (p->DBI_R_onoff[p->dram_fsp] << 6));
@@ -295,14 +295,14 @@ void DFSRuntimeMRW_preset(DRAMC_CTX_T *p, U8 sram_shu_level)
 		P_Fld(u1MR02Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_1) |
 		P_Fld(u1MR03_Value, LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_2) |
 		P_Fld(u1MR11Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_0_MR_OP_SET_SHU_0_3));
-		//Darren-mcSHOW_DBG_MSG(("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR1 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03Value[p->dram_fsp], u1MR11Value[p->dram_fsp]));
+		//Darren-msg("\tMR01 = 0x%x, MR02 = 0x%x, MR03 = 0x%x, MR1 = 0x%x\n", u1MR01Value[p->dram_fsp], u1MR02Value[p->dram_fsp], u1MR03Value[p->dram_fsp], u1MR11Value[p->dram_fsp]);
 
 	//! save shux mr22/mr51
 	vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_0_1 + (sram_shu_level << 4),
 		P_Fld(u1MR21Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_5) |
 		P_Fld(u1MR22Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_6) |
 		P_Fld(u1MR51Value[p->dram_fsp], LPIF_MR_OP_STORE_SHU_0_1_MR_OP_SET_SHU_0_7));
-		//Darren-mcSHOW_DBG_MSG(("\tMR22 = 0x%x, MR51 = 0x%x\n", u1MR22Value[p->dram_fsp], u1MR51Value[p->dram_fsp]));
+		//Darren-msg("\tMR22 = 0x%x, MR51 = 0x%x\n", u1MR22Value[p->dram_fsp], u1MR51Value[p->dram_fsp]);
 
 	//! save shux mr12/mr14
 	vIO32WriteFldMulti_All(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_0 + (sram_shu_level << 4),
@@ -322,7 +322,7 @@ void DFSRuntimeMRW_preset(DRAMC_CTX_T *p, U8 sram_shu_level)
 	{
 		for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
 		{
-			mcSHOW_DBG_MSG(("\tCH%d, RK%d, MR12 = 0x%x, MR14 = 0x%x\n", u1ChIdx, u1RankIdx,u1MR12Value[u1ChIdx][u1RankIdx][p->dram_fsp], u1MR14Value[u1ChIdx][u1RankIdx][p->dram_fsp]));
+			msg("\tCH%d, RK%d, MR12 = 0x%x, MR14 = 0x%x\n", u1ChIdx, u1RankIdx,u1MR12Value[u1ChIdx][u1RankIdx][p->dram_fsp], u1MR14Value[u1ChIdx][u1RankIdx][p->dram_fsp]);
 		}
 	}
 #endif
@@ -539,7 +539,7 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev
 		md32_rtmrw_rank = 0x1; //! single rank
 #endif
 
-	//Darren-mcSHOW_DBG_MSG(("[DFSRuntimeMRWEn]\n"));
+	//Darren-msg("[DFSRuntimeMRWEn]\n");
 	u1FldIdx = 0; // shift 8-bits field
 	for (u1ChIdx = ch_start; u1ChIdx < ch_end; u1ChIdx++)
 	{
@@ -549,12 +549,12 @@ static void DFSRuntimeMRWEn(DRAMC_CTX_T *p, U8 cur_shu_mux_index, U8 nxt_shu_lev
 
 		for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
 		{
-			//Darren-mcSHOW_DBG_MSG(("CH%d RK%d\n", u1ChIdx, u1RankIdx));
+			//Darren-msg("CH%d RK%d\n", u1ChIdx, u1RankIdx);
 			//! get shux mr12/mr14/
 			rtmr12 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_0 + (nxt_shu_level << 4),  Fld(8, u1FldIdx*8));
 			rtmr14 = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_MR_OP_STORE_SHU_7_1 + (nxt_shu_level << 4),  Fld(8, u1FldIdx*8));
-			//Darren-mcSHOW_DBG_MSG(("\tMR1=0x%x, MR2=0x%x, MR3=0x%x, MR11=0x%x\n", rtmr1, rtmr2, rtmr3, rtmr11));
-			//Darren-mcSHOW_DBG_MSG(("\tMR12=0x%x, MR13=0x%x, MR14=0x%x, MR22=0x%x, MR51=0x%x\n", rtmr12, rtmr13, rtmr14, rtmr22, rtmr51));
+			//Darren-msg("\tMR1=0x%x, MR2=0x%x, MR3=0x%x, MR11=0x%x\n", rtmr1, rtmr2, rtmr3, rtmr11);
+			//Darren-msg("\tMR12=0x%x, MR13=0x%x, MR14=0x%x, MR22=0x%x, MR51=0x%x\n", rtmr12, rtmr13, rtmr14, rtmr22, rtmr51);
 			TriggerRTMRW_SingleChannel(p, u1RankIdx, rtmr1, rtmr2, rtmr3, rtmr11, rtmr12, rtmr13, rtmr14, rtmr21, rtmr22, rtmr51);
 			u1FldIdx++; // shift 8-bits field
 		}
@@ -643,7 +643,7 @@ void WaitDFSDebugSM(DRAMC_CTX_T *p, U8 u1HangStatus)
 		do {
 			u1Status[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_DVFS_STATUS), DVFS_STATUS_CUT_PHY_ST_SHU);
 			u1DvfsState[u1ChIdx] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRR_STATUS2), MRR_STATUS2_DVFS_STATE);
-			//mcSHOW_DBG_MSG(("[WaitDFSDebugSM] CH%d DFS debug mode state (0x%x, 0x%x), Dvfs State = 0x%x\n", u1ChIdx, u1Status[u1ChIdx], u1HangStatus, u1DvfsState[u1ChIdx]));
+			//msg("[WaitDFSDebugSM] CH%d DFS debug mode state (0x%x, 0x%x), Dvfs State = 0x%x\n", u1ChIdx, u1Status[u1ChIdx], u1HangStatus, u1DvfsState[u1ChIdx]);
 			if (u1Status[u1ChIdx] == u1HangStatus)
 				break;
 
@@ -674,7 +674,7 @@ void ExitDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
 	}
 	else
 	{
-		mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
+		err("DFS debug mode err!\n");
 		#if __ETT__
 		while (1);
 		#endif
@@ -715,7 +715,7 @@ void ChkDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
 	}
 	else
 	{
-		mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
+		err("DFS debug mode err!\n");
 		#if __ETT__
 		while (1);
 		#endif
@@ -745,7 +745,7 @@ void EntryDFSDebugMode(DRAMC_CTX_T *p, DFS_DBG_T eDbgMode)
 	}
 	else
 	{
-		mcSHOW_ERR_MSG(("DFS debug mode err!\n"));
+		err("DFS debug mode err!\n");
 		#if __ETT__
 		while (1);
 		#endif
@@ -805,7 +805,7 @@ static void NoQueueFlushWA(DRAMC_CTX_T *p, U8 u1WA_enable)
 		u4PERFCTL0_backup = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_PERFCTL0)) >> Fld_shft(PERFCTL0_RWAGEEN)) & 0x3;
 		vIO32WriteFldMulti(DRAMC_REG_PERFCTL0, P_Fld(0, PERFCTL0_RWAGEEN)
 				| P_Fld(0, PERFCTL0_EMILLATEN));
-		//mcSHOW_DBG_MSG(("[NoQueueFlushWA] PERFCTL0[11:10] backup = 0x%x\n", u4PERFCTL0_backup));
+		//msg("[NoQueueFlushWA] PERFCTL0[11:10] backup = 0x%x\n", u4PERFCTL0_backup);
 	}
 	else
 	{
@@ -857,7 +857,7 @@ void TxReadBaseODTWA(DRAMC_CTX_T *p, U8 next_shu_level)
 	else
 		termen_dis = ENABLE; // un-term
 
-	//mcSHOW_DBG_MSG(("[TxReadBaseODTWA] SRAM SHU%d, termen_dis = %d\n", next_shu_level, termen_dis));
+	//msg("[TxReadBaseODTWA] SRAM SHU%d, termen_dis = %d\n", next_shu_level, termen_dis);
 	vIO32WriteFldAlign(DDRPHY_REG_B0_DQ6, termen_dis, B0_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B0);
 	vIO32WriteFldAlign(DDRPHY_REG_B1_DQ6, termen_dis, B1_DQ6_RG_TX_ARDQ_ODTEN_EXT_DIS_B1);
 	vIO32WriteFldAlign(DDRPHY_REG_CA_CMD6, termen_dis, CA_CMD6_RG_TX_ARCMD_ODTEN_EXT_DIS);
@@ -929,7 +929,7 @@ void DPHYSaveToSRAMShuWA(DRAMC_CTX_T *p, U8 sram_shu_level)
 
 			u4PHY_VREF_SEL = (u4B1_PHY_VREF_SEL<<16) | u4B0_PHY_VREF_SEL;
 
-			mcSHOW_DBG_MSG(("[DPHYSaveToSRAMShuWA] CH%d RK%d, B1B0_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u4PHY_VREF_SEL));
+			msg("[DPHYSaveToSRAMShuWA] CH%d RK%d, B1B0_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u4PHY_VREF_SEL);
 			p->ShuRGAccessIdx = DRAM_DFS_REG_SHU0;
 			vIO32Write4B(DRAMC_REG_ADDR(gSRAMBackupIdx[sram_shu_level][u1RankIdx]), u4PHY_VREF_SEL);
 		}
@@ -960,7 +960,7 @@ void DPHYSRAMShuWAToSHU1(DRAMC_CTX_T *p)
 			u4B1_PHY_VREF_SEL = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset));
 
 			u4PHY_VREF_SEL = (u4B1_PHY_VREF_SEL<<16) | u4B0_PHY_VREF_SEL;
-			mcSHOW_DBG_MSG(("[DPHYRxVrefWAToSHU1] CH%d RK%d, B1B0_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u4PHY_VREF_SEL));
+			msg("[DPHYRxVrefWAToSHU1] CH%d RK%d, B1B0_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u4PHY_VREF_SEL);
 
 			p->ShuRGAccessIdx = DRAM_DFS_REG_SHU1;
 			u4Offset = 0; // B0
@@ -999,7 +999,7 @@ void SRAMShuRestoreToDPHYWA(DRAMC_CTX_T *p, U8 sram_shu_level, U8 pingpong_shu_l
 				u4Offset = u1ByteIdx*DDRPHY_AO_B0_B1_OFFSET;
 				u4Byte_PHY_VREF_SEL = (u4PHY_VREF_SEL >> (16*u1ByteIdx)) & 0xffff;
 
-				//mcSHOW_DBG_MSG(("[SRAMShuRestoreToDPHYWA] CH%d RK%d B%d, u4Byte_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u1ByteIdx, u4Byte_PHY_VREF_SEL));
+				//msg("[SRAMShuRestoreToDPHYWA] CH%d RK%d B%d, u4Byte_PHY_VREF_SEL=0x%x\n", u1ChannelIdx, u1RankIdx, u1ByteIdx, u4Byte_PHY_VREF_SEL);
 
 				p->ShuRGAccessIdx = pingpong_shu_level;
 				vIO32Write4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_PHY_VREF_SEL+u4Offset), u4Byte_PHY_VREF_SEL);
@@ -1057,7 +1057,7 @@ void DVFSSettings(DRAMC_CTX_T *p)
 
 	// @Darren, set current SRAM SHU index for SPM mode DFS latch/restore
 	vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, vGet_Current_ShuLevel(p), MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL_SRAM);
-	//mcSHOW_DBG_MSG(("[DVFSSettings] SHU_LEVEL_SRAM = %d\n", vGet_Current_ShuLevel(p)));
+	//msg("[DVFSSettings] SHU_LEVEL_SRAM = %d\n", vGet_Current_ShuLevel(p));
 
 #if (fcFOR_CHIP_ID == fcA60868) // @Darren, for A60868 only
 	for (u1Channel = CHANNEL_A; u1Channel < p->support_channel_num; u1Channel++)
@@ -1293,13 +1293,13 @@ void DPMInit(DRAMC_CTX_T *p)
 
 	if (p->u1PLLMode == PHYPLL_MODE)
 	{
-		mcSHOW_DBG_MSG(("PHYPLL\n"));
+		msg("PHYPLL\n");
 		u1Pll1Val = u1SetVal;
 		u1Pll2Val = 0;
 	}
 	else
 	{
-		mcSHOW_DBG_MSG(("CLRPLL\n"));
+		msg("CLRPLL\n");
 		u1Pll1Val = 0;
 		u1Pll2Val = u1SetVal;
 	}
@@ -1394,11 +1394,11 @@ void TransferPLLToSPMControl(DRAMC_CTX_T *p, U32 MD32Offset)
 		| P_Fld(1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW) // 1: MD32 RG mode, 0: MD32 PST mode
 		| P_Fld(1, LPIF_FSM_CFG_1_LPIF_OUTPUT_PATH_FROM_SW_2ND));*/ // 1: MD32 RG mode, 0: MD32 PST mode
 
-	mcSHOW_DBG_MSG(("TransferPLLToSPMControl - MODE SW "));
+	msg("TransferPLLToSPMControl - MODE SW ");
 
 	if (p->u1PLLMode == PHYPLL_MODE)
 	{
-		/*mcSHOW_DBG_MSG(("PHYPLL\n"));
+		/*msg("PHYPLL\n");
 		vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
 		vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);  // PHYPLL for part of SHU RG
 		vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_MODE_SW); // same as DRAMC_DPY_CLK_SW_CON2_SW_PHYPLL2_MODE_SW by MUX
@@ -1414,7 +1414,7 @@ void TransferPLLToSPMControl(DRAMC_CTX_T *p, U32 MD32Offset)
 	}
 	else
 	{
-		/*mcSHOW_DBG_MSG(("CLRPLL\n"));
+		/*msg("CLRPLL\n");
 		vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
 		vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);  // CLRPLL for part of SHU RG
 		vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0+MD32Offset, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // same as DRAMC_DPY_CLK_SW_CON2_SW_PHYPLL2_MODE_SW by MUX
@@ -1437,7 +1437,7 @@ void TransferPLLToSPMControl(DRAMC_CTX_T *p, U32 MD32Offset)
 	// @Darren for MD32 RG mode only
 	// MD32 PST mode shuffle level = (LPIF_CTRL_CTRL1_LPIF_DRAMC_DR_SHU_LEVEL_SRAM | LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL)
 	//Darren-vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1+MD32Offset, u2SramLevel, LPIF_LOW_POWER_CFG_1_DR_SHU_SRAM_LEVEL);
-	//mcSHOW_DBG_MSG(("TransferPLLToSPMControl - Current SRAM SHU LEVEL = %d\n", u1CurrShuLevel));
+	//msg("TransferPLLToSPMControl - Current SRAM SHU LEVEL = %d\n", u1CurrShuLevel);
 
 #if DFS_NOQUEUE_FLUSH_WA
 	// Enable Max cnt for latency measure from shu_en to shu_ack
@@ -1497,11 +1497,11 @@ void DFSBypassMR13HwSet(DRAMC_CTX_T *p)
 				TransferReg.u4Fld = BYPASS_FSPOP_BPFSP_SET_SHU9;
 				break;
 			default:
-				mcSHOW_ERR_MSG(("[DFSBypassMR13HwSet] fail at BPFSP_SHU%d incorrect !!!\n", u1SramShuIdx));
+				err("[DFSBypassMR13HwSet] fail at BPFSP_SHU%d incorrect !!!\n", u1SramShuIdx);
 				break;
 		}
 		BFSP = (gFreqTbl[u1ShuffleIdx].freq_sel <= LP4_DDR2667)? 0x1: 0x0; //0x1 (Bypass), 0x0 (Not bypass)
-		//mcSHOW_DBG_MSG(("[DFSBypassMR13HwSet] BPFSP_SHU%d = 0x%x\n", u1SramShuIdx, BFSP));
+		//msg("[DFSBypassMR13HwSet] BPFSP_SHU%d = 0x%x\n", u1SramShuIdx, BFSP);
 		vIO32WriteFldAlign_All(TransferReg.u4Addr, BFSP, TransferReg.u4Fld);
 	}
 	vIO32WriteFldAlign_All(DRAMC_REG_TX_FREQ_RATIO_OLD_MODE0, 0x1, TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT); // 1: shuffle level = 10, 0: shuffle level =4
@@ -1545,7 +1545,7 @@ void DramcSaveToShuffleSRAM(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_
 		do {
 			u1value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_SRAM_DONE);
 			u1value |= (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_APB_DONE) << 1);
-			mcSHOW_DBG_MSG3(("\twait dramc to shuffle sram done.\n"));
+			msg3("\twait dramc to shuffle sram done.\n");
 		} while (u1value != 0x3);
 		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
 		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
@@ -1579,7 +1579,7 @@ void LoadShuffleSRAMtoDramc(DRAMC_CTX_T *p, DRAM_DFS_SHUFFLE_TYPE_T srcRG, DRAM_
 		do {
 			u1value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_SRAM_DONE);
 			u1value |= (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DMA_DEBUG0), MISC_DMA_DEBUG0_APB_DONE) << 1);
-			mcSHOW_DBG_MSG3(("\twait shuffle sram to dramc done.\n"));
+			msg3("\twait shuffle sram to dramc done.\n");
 		} while (u1value != 0x3);
 		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_DMA_FIRE);
 		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SRAM_DMA0), 0, MISC_SRAM_DMA0_SW_STEP_EN_MODE);
@@ -1600,7 +1600,7 @@ static U8 WaitChShuEnAck(DRAMC_CTX_T *p, U32 u4Addr, U32 u4Fld, U8 u1Status)
 
 		do {
 			u1WaitShuAckState = u4IO32ReadFldAlign(DRAMC_REG_ADDR(u4Addr), u4Fld);
-			//mcSHOW_DBG_MSG(("[WaitChShuEnAck] Wait Shu Ack State = 0x%x\n", u1WaitShuAckState));
+			//msg("[WaitChShuEnAck] Wait Shu Ack State = 0x%x\n", u1WaitShuAckState);
 			if (u1WaitShuAckState == u1Status)
 				break;
 		} while(1);
@@ -1620,12 +1620,12 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 
 	if (p->u1PLLMode == PHYPLL_MODE)
 	{
-		mcSHOW_DBG_MSG3(("Disable CLRPLL\n"));
+		msg3("Disable CLRPLL\n");
 		vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN);
 	}
 	else
 	{
-		mcSHOW_DBG_MSG3(("Disable PHYPLL\n"));
+		msg3("Disable PHYPLL\n");
 		vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN);
 	}
 
@@ -1636,11 +1636,11 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 
 	if (p->u1PLLMode == PHYPLL_MODE)
 	{
-		mcSHOW_DBG_MSG3(("DFSDirectJump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+		msg3("DFSDirectJump to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck);
 	}
 	else
 	{
-		mcSHOW_DBG_MSG3(("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+		msg3("DFSDirectJump to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck);
 	}
 
 	/*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/
@@ -1656,14 +1656,14 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, !p->u1PLLMode, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
-		mcSHOW_DBG_MSG3(("Enable CLRPLL\n"));
+		msg3("Enable CLRPLL\n");
 	}
 	else
 	{
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, !p->u1PLLMode, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
-		mcSHOW_DBG_MSG3(("Enable PHYPLL\n"));
+		msg3("Enable PHYPLL\n");
 	}
 	mcDELAY_US(1);
 
@@ -1678,7 +1678,7 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 	while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK, u1ChkComplete) != u1ShuAck)
 	//while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_LOAD_ACK))
 	{
-		mcSHOW_DBG_MSG3(("\twait sram load ack.\n"));
+		msg3("\twait sram load ack.\n");
 	}
 	vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_LOAD);
 #endif
@@ -1713,17 +1713,17 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 #endif
 
 #if 0
-	mcSHOW_DBG_MSG3(("Enable SHORT-QUEUE\n"));
+	msg3("Enable SHORT-QUEUE\n");
 	vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
 
-	mcSHOW_DBG_MSG3(("\twait 5us for short queue ack.\n"));
+	msg3("\twait 5us for short queue ack.\n");
 	mcDELAY_US(5);
 #endif
 
-	//mcSHOW_DBG_MSG(("Disable RX-Tracking\n"));
+	//msg("Disable RX-Tracking\n");
 	//vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN);
 
-	mcSHOW_DBG_MSG3(("SHUFFLE Start\n"));
+	msg3("SHUFFLE Start\n");
 	vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from SHU_EN=1 to ACK, DV spec < 5.1us
 
 #if DFS_NOQUEUE_FLUSH_WA && ENABLE_DFS_NOQUEUE_FLUSH_DBG
@@ -1732,7 +1732,7 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 
 	// Fixed DV sim spec for DFS shu_en=1 < 5.1us and shu_en=0 < 120ns
 #if 1//Darren-for test chip(FOR_DV_SIMULATION_USED == 0 && SW_CHANGE_FOR_SIMULATION == 0)
-	//mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n"));
+	//msg3("\twait 5us for shu_en ack.\n");
 	//mcDELAY_US(5);
 	#if 0//ENABLE_DFS_DEBUG_MODE
 	ChkDFSDebugMode(p, CHG_CLK_MODE);
@@ -1746,7 +1746,7 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 #endif
 	)
 	{
-		mcSHOW_DBG_MSG3(("\twait shu_en ack.\n"));
+		msg3("\twait shu_en ack.\n");
 	}
 #else
 	while (u4IO32ReadFldAlign(DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE) != u1ShuAckState); // SHUFFLE_END
@@ -1766,11 +1766,11 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 
 	//vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
 	vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN); // NOTE: from ACK to SHU_EN=0, DV spec < 120ns
-	mcSHOW_DBG_MSG3(("SHUFFLE End\n"));
+	msg3("SHUFFLE End\n");
 
 	//if(shu_level == 0)//LP4-2CH
 	//{
-		//mcSHOW_DBG_MSG(("Enable RX-Tracking for shuffle-0\n"));
+		//msg("Enable RX-Tracking for shuffle-0\n");
 		//vIO32WriteFldAlign(SPM_SW_RSV_8, 3, SW_RSV_8_RX_TRACKING_EN);
 	//}
 
@@ -1793,7 +1793,7 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 	while (WaitChShuEnAck(p, DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK, u1ChkComplete) != u1ShuAck)
 	//while (!u4IO32ReadFldAlign(DDRPHY_REG_MISC_DMA_DEBUG0, MISC_DMA_DEBUG0_SC_DR_SRAM_RESTORE_ACK))
 	{
-		mcSHOW_DBG_MSG3(("\twait sram restore ack.\n"));
+		msg3("\twait sram restore ack.\n");
 	}
 	vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SRAM_RESTORE);
 
@@ -1809,7 +1809,7 @@ void DramcDFSDirectJump_SRAMShuRGMode(DRAMC_CTX_T *p, U8 shu_level)
 	TimingTxsrWA(p, shu_level);
 	#endif
 
-	mcSHOW_DBG_MSG3(("Shuffle flow complete\n"));
+	msg3("Shuffle flow complete\n");
 
 	p->u1PLLMode = !p->u1PLLMode;
 	return;
@@ -1824,12 +1824,12 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level)
 
 	if (p->u1PLLMode == PHYPLL_MODE)
 	{
-		mcSHOW_DBG_MSG3(("Disable CLRPLL\n"));
+		msg3("Disable CLRPLL\n");
 		vIO32WriteFldAlign_All(DDRPHY_REG_CLRPLL0, 0, CLRPLL0_RG_RCLRPLL_EN);
 	}
 	else
 	{
-		mcSHOW_DBG_MSG3(("Disable PHYPLL\n"));
+		msg3("Disable PHYPLL\n");
 		vIO32WriteFldAlign_All(DDRPHY_REG_PHYPLL0, 0, PHYPLL0_RG_RPHYPLL_EN);
 	}
 
@@ -1840,11 +1840,11 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level)
 
 	if (p->u1PLLMode == PHYPLL_MODE)
 	{
-		mcSHOW_DBG_MSG3(("DFSDirectJump_RGMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+		msg3("DFSDirectJump_RGMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck);
 	}
 	else
 	{
-		mcSHOW_DBG_MSG3(("DFSDirectJump_RGMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+		msg3("DFSDirectJump_RGMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck);
 	}
 
 	/*TINFO="DRAM : set ddrphy_fb_ck_en=1"*/
@@ -1860,14 +1860,14 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level)
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, u1shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
-		mcSHOW_DBG_MSG3(("Enable CLRPLL\n"));
+		msg3("Enable CLRPLL\n");
 	}
 	else
 	{
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN);
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, u1shu_level, MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL);
 		vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN);
-		mcSHOW_DBG_MSG3(("Enable PHYPLL\n"));
+		msg3("Enable PHYPLL\n");
 	}
 	mcDELAY_US(1);
 
@@ -1889,21 +1889,21 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level)
 #endif
 
 #if 0
-	mcSHOW_DBG_MSG3(("Enable SHORT-QUEUE\n"));
+	msg3("Enable SHORT-QUEUE\n");
 	vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 1, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
 
-	mcSHOW_DBG_MSG3(("\twait 5us for short queue ack.\n"));
+	msg3("\twait 5us for short queue ack.\n");
 	mcDELAY_US(5);
 #endif
 
-	//mcSHOW_DBG_MSG(("Disable RX-Tracking\n"));
+	//msg("Disable RX-Tracking\n");
 	//vIO32WriteFldAlign(SPM_SW_RSV_8, 0, SW_RSV_8_RX_TRACKING_EN);
 
 
-	mcSHOW_DBG_MSG3(("SHUFFLE Start\n"));
+	msg3("SHUFFLE Start\n");
 	vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 1, MISC_RG_DFS_CTRL_RG_DR_SHU_EN);
 
-	//mcSHOW_DBG_MSG3(("\twait 5us for shu_en ack.\n"));
+	//msg3("\twait 5us for shu_en ack.\n");
 	//mcDELAY_US(5);
 	//while (WaitChShuEnAck(p, DRAMC_REG_MRR_STATUS2, MRR_STATUS2_DVFS_STATE, u1ShuAckState) != u1ShuAck) // SHUFFLE_END
 	//@tg Fix RG mode can not recevie shuffle end ack.
@@ -1913,16 +1913,16 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level)
 #endif
 	)
 	{
-		mcSHOW_DBG_MSG3(("\twait shu_en ack.\n"));
+		msg3("\twait shu_en ack.\n");
 	}
 
 	//vIO32WriteFldAlign(DDRPHY_MISC_SPM_CTRL1, 0, MISC_SPM_CTRL1_RG_DR_SHORT_QUEUE);
 	vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DR_SHU_EN);
-	mcSHOW_DBG_MSG3(("SHUFFLE End\n"));
+	msg3("SHUFFLE End\n");
 
 	//if(shu_level == 0)//LP4-2CH
 	//{
-		//mcSHOW_DBG_MSG(("Enable RX-Tracking for shuffle-0\n"));
+		//msg("Enable RX-Tracking for shuffle-0\n");
 		//vIO32WriteFldAlign(SPM_SW_RSV_8, 3, SW_RSV_8_RX_TRACKING_EN);
 	//}
 
@@ -1942,7 +1942,7 @@ void DramcDFSDirectJump_RGMode(DRAMC_CTX_T *p, U8 shu_level)
 	/*TINFO="DRAM : set ddrphy_fb_ck_en=0"*/
 	vIO32WriteFldAlign_All(DDRPHY_REG_MISC_RG_DFS_CTRL, 0, MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN);
 
-	mcSHOW_DBG_MSG3(("Shuffle flow complete\n"));
+	msg3("Shuffle flow complete\n");
 
 	p->u1PLLMode = !p->u1PLLMode;
 	return;
@@ -1967,11 +1967,11 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 
 	if (p->u1PLLMode == PHYPLL_MODE)
 	{
-		mcSHOW_DBG_MSG3(("DramcDFSDirectJump_SPMMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+		msg3("DramcDFSDirectJump_SPMMode to CLRPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck);
 	}
 	else
 	{
-		mcSHOW_DBG_MSG3(("DramcDFSDirectJump_SPMMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck));
+		msg3("DramcDFSDirectJump_SPMMode to PHYPLL, SHU_LEVEL=%d, ACK=%x\n", shu_level, u1ShuAck);
 	}
 
 	//vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x1, MISC_STBCAL2_STB_DBG_STATUS); // HJ Huang
@@ -1984,7 +1984,7 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 	//LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[1:0] for CHA
 	//LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL[3:2] for CHB
 	pingpong_shu_level = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_STATUS_10, LPIF_STATUS_10_DRAMC_DR_SHU_LEVEL); // read shuffle level for dramc conf0/1
-	mcSHOW_DBG_MSG3(("Ping-pong CONF%d\n", (pingpong_shu_level & 0x1)));
+	msg3("Ping-pong CONF%d\n", (pingpong_shu_level & 0x1));
 	for (i = 0; i < DPM_CH_NUM; i++)
 	{
 		u2SramLevel |= (shu_level << (i*4));
@@ -1997,14 +1997,14 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 		vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
 		vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, pingpong_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
 		vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
-		mcSHOW_DBG_MSG3(("Enable CLRPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel));
+		msg3("Enable CLRPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel);
 	}
 	else
 	{
 		vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL2_SHU_EN);
 		vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, pingpong_shu_level, LPIF_LOW_POWER_CFG_1_DR_SHU_LEVEL);
 		vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_PHYPLL_SHU_EN);
-		mcSHOW_DBG_MSG3(("Enable PHYPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel));
+		msg3("Enable PHYPLL (0x%x 0x%x)\n", pingpong_shu_level, u2SramLevel);
 	}
 	mcDELAY_US(1);
 
@@ -2024,7 +2024,7 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 #endif
 	)
 	{
-		mcSHOW_DBG_MSG3(("\twait sram load ack.\n"));
+		msg3("\twait sram load ack.\n");
 	}
 	vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_DR_SRAM_LOAD);
 #endif
@@ -2089,7 +2089,7 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 	SPMTx_Track_Retry_OnOff(p, shu_level, ENABLE);
 #endif
 
-	mcSHOW_DBG_MSG3(("SHUFFLE Start\n"));
+	msg3("SHUFFLE Start\n");
 	//vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x3, MISC_STBCAL2_STB_DBG_STATUS);
 	vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, u1EnMd32Ch, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
 
@@ -2105,13 +2105,13 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 #endif
 	)
 	{
-		mcSHOW_DBG_MSG3(("\twait shu_en ack.\n"));
+		msg3("\twait shu_en ack.\n");
 	}
 
 #if DFS_NOQUEUE_FLUSH_LATENCY_CNT
 	U8 MaxCnt = u4IO32ReadFldAlign(DDRPHY_MD32_REG_LPIF_RESERVED_6, LPIF_RESERVED_6_MAX_CNT_SHU_EN_HIGH_TO_ACK); // show chx max cnt
 	// cnt * 8 * 4.8ns (208M)
-	mcSHOW_DBG_MSG(("\tMAX CNT = %d\n", MaxCnt));
+	msg("\tMAX CNT = %d\n", MaxCnt);
 #endif
 
 #if ENABLE_TX_REBASE_WDQS_DQS_PI_WA
@@ -2123,7 +2123,7 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 #endif
 	vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_DR_SHU_EN);
 	//vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x4, MISC_STBCAL2_STB_DBG_STATUS);
-	mcSHOW_DBG_MSG3(("SHUFFLE End\n"));
+	msg3("SHUFFLE End\n");
 
 	if (p->u1PLLMode == PHYPLL_MODE)
 		vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_0, 0, LPIF_LOW_POWER_CFG_0_PHYPLL_MODE_SW); // PHYPLL off
@@ -2151,7 +2151,7 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 #endif
 	)
 	{
-		mcSHOW_DBG_MSG3(("\twait sram restore ack.\n"));
+		msg3("\twait sram restore ack.\n");
 	}
 	vIO32WriteFldAlign_All(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_2, 0, LPIF_LOW_POWER_CFG_2_DR_SRAM_RESTORE);
 #endif
@@ -2174,7 +2174,7 @@ static void DramcDFSDirectJump_SPMMode(DRAMC_CTX_T *p, U8 shu_level)
 	p->u1PLLMode = !p->u1PLLMode;
 
 	//vIO32WriteFldAlign(DDRPHY_REG_MISC_STBCAL2, 0x5, MISC_STBCAL2_STB_DBG_STATUS);
-	mcSHOW_DBG_MSG3(("Shuffle flow complete\n"));
+	msg3("Shuffle flow complete\n");
 
 	return;
 }
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c
index b503498dd0..100d65b32b 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_lowpower.c
@@ -678,7 +678,7 @@ void EnableDramcPhyDCM(DRAMC_CTX_T *p, bool bEn)
 
 #if ((CHECK_GOLDEN_SETTING == TRUE) && (APPLY_LOWPOWER_GOLDEN_SETTINGS == 0))
 	DRAM_STATUS_T stResult = CheckGoldenSetting(p);
-	mcSHOW_DBG_MSG(("Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG")));
+	msg("Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG"));
 #endif
 
 	DramcBroadcastOnOff(u4WbrBackup);
@@ -698,65 +698,65 @@ DRAM_STATUS_T CheckRxPICGNewModeSetting(DRAMC_CTX_T *p)
 	for(channel_idx = CHANNEL_A; channel_idx < p->support_channel_num; channel_idx++)
 	{
 		p->channel = channel_idx;
-		mcSHOW_DBG_MSG(("CH[%d] \n", channel_idx));
+		msg("CH[%d] \n", channel_idx);
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_MCK);
-		mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_MCK:0x%x \n", u4Value));
+		msg("MISC_CTRL4_R_OPT2_CG_MCK:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_MPDIV_CG);
-		mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_MPDIV_CG:0x%x \n", u4Value));
+		msg("MISC_CTRL4_R_OPT2_MPDIV_CG:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_CTRL4), MISC_CTRL4_R_OPT2_CG_DQSIEN);
-		mcSHOW_DBG_MSG(("MISC_CTRL4_R_OPT2_CG_DQSIEN:0x%x \n", u4Value));
+		msg("MISC_CTRL4_R_OPT2_CG_DQSIEN:0x%x \n", u4Value);
 
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL1), MISC_STBCAL1_STBCNT_SHU_RST_EN);
-		mcSHOW_DBG_MSG(("MISC_STBCAL1_STBCNT_SHU_RST_EN:0x%x \n", u4Value));
+		msg("MISC_STBCAL1_STBCNT_SHU_RST_EN:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN);
-		mcSHOW_DBG_MSG(("MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN:0x%x \n", u4Value));
+		msg("MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_STBCAL), MISC_SHU_STBCAL_DQSIEN_PICG_MODE);
-		mcSHOW_DBG_MSG(("MISC_SHU_STBCAL_DQSIEN_PICG_MODE:0x%x \n", u4Value));
+		msg("MISC_SHU_STBCAL_DQSIEN_PICG_MODE:0x%x \n", u4Value);
 
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT);
-		mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT:0x%x \n", u4Value));
+		msg("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT);
-		mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT:0x%x \n", u4Value));
+		msg("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBCAL2), MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN);
-		mcSHOW_DBG_MSG(("MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN:0x%x \n", u4Value));
+		msg("MISC_STBCAL2_STB_STBENRST_EARLY_1T_EN:0x%x \n", u4Value);
 
 		for (u1RankIdx = 0; u1RankIdx < p->support_rank_num; u1RankIdx++)//Should set 2 rank
 		{
 
 			vSetRank(p, u1RankIdx);
 			u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT);
-			mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT:0x%x \n", u1RankIdx, u4Value));
+			msg("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT:0x%x \n", u1RankIdx, u4Value);
 			u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSIEN_PICG_CTRL), MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT);
-			mcSHOW_DBG_MSG(("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT:0x%x \n", u1RankIdx, u4Value));
+			msg("Rank[%d] MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT:0x%x \n", u1RankIdx, u4Value);
 		}
 		vSetRank(p, RANK_0);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN);
-		mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN:0x%x \n", u4Value));
+		msg("MISC_RX_IN_BUFF_EN_CTRL_DIS_IN_BUFF_EN:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN);
-		mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN:0x%x \n", u4Value));
+		msg("MISC_RX_IN_BUFF_EN_CTRL_FIX_IN_BUFF_EN:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_BUFF_EN_CTRL), MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN);
-		mcSHOW_DBG_MSG(("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN:0x%x \n", u4Value));
+		msg("MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_4BYTE_EN:0x%x \n", u4Value);
 
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN);
-		mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN:0x%x \n", u4Value));
+		msg("MISC_RX_IN_GATE_EN_CTRL_DIS_IN_GATE_EN:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN);
-		mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN:0x%x \n", u4Value));
+		msg("MISC_RX_IN_GATE_EN_CTRL_FIX_IN_GATE_EN:0x%x \n", u4Value);
 
 		u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_RX_IN_GATE_EN_CTRL), MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN);
-		mcSHOW_DBG_MSG(("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN:0x%x \n", u4Value));
+		msg("MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_4BYTE_EN:0x%x \n", u4Value);
 
 	}
 	p->channel = CHANNEL_A;
@@ -780,7 +780,7 @@ DRAM_STATUS_T CheckGoldenField(DRAMC_CTX_T *p, GOLDEN_FIELD_T *golden_setting_an
 		{
 			vSetPHY2ChannelMapping(p, channel_idx);
 			u4Value = u4IO32ReadFldAlign(DRAMC_REG_ADDR(golden_setting_anwer[u2Idx].group), golden_setting_anwer[u2Idx].field);
-			//mcSHOW_DBG_MSG(("%s: 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Value));
+			//msg("%s: 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Value);
 
 			u4Answer = *(&golden_setting_anwer[u2Idx].u4ChaValue);//golden_setting_anwer only has CHA value
 
@@ -788,11 +788,11 @@ DRAM_STATUS_T CheckGoldenField(DRAMC_CTX_T *p, GOLDEN_FIELD_T *golden_setting_an
 			{
 				if(u4Answer == u4Value)
 				{
-					//mcSHOW_DBG_MSG(("OK [%s] 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Answer));
+					//msg("OK [%s] 0x%x\n", golden_setting_anwer[u2Idx].fieldName, u4Answer);
 				}
 				else
 				{
-					mcSHOW_DBG_MSG(("*** fail ***[%s]CH[%d][0x%x][ANS:0x%x]****** fail\n", golden_setting_anwer[u2Idx].fieldName, channel_idx, u4Value, u4Answer));
+					msg("*** fail ***[%s]CH[%d][0x%x][ANS:0x%x]****** fail\n", golden_setting_anwer[u2Idx].fieldName, channel_idx, u4Value, u4Answer);
 					eStatus |= DRAM_FAIL;
 				}
 			}
@@ -809,7 +809,7 @@ DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p)
 	U8 backup_channel = vGetPHY2ChannelMapping(p);
 	DRAM_STATUS_T eStatus = DRAM_OK;
 
-	mcSHOW_DBG_MSG(("Golden setting check[Begin]\n"));
+	msg("Golden setting check[Begin]\n");
 	eStatus |= CheckGoldenField(p, nonshuf_golden_setting_anwer, sizeof(nonshuf_golden_setting_anwer));
 
 
@@ -819,16 +819,16 @@ DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p)
 		{
 			if (u1ShuffleIdx < DRAM_DFS_SRAM_MAX)
 			{
-				mcSHOW_DBG_MSG(("SRAM SHU%d\n", u1ShuffleIdx));
+				msg("SRAM SHU%d\n", u1ShuffleIdx);
 				u1SramShuffleIdx = u1ShuffleIdx;
 			}
 			else
 			{
-				mcSHOW_DBG_MSG(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
+				msg("CONF SHU0, DDR[%d]\n", p->frequency * 2);
 				u1SramShuffleIdx = u1BkShuffleIdx; //Restore to original freq && check conf SHU0
 			}
 
-			//mcSHOW_DBG_MSG(("shuf_golden_setting_anwer:%d %d\n",	sizeof(shuf_golden_setting_anwer), sizeof(shuf_golden_setting_anwer[0])));
+			//msg("shuf_golden_setting_anwer:%d %d\n",	sizeof(shuf_golden_setting_anwer), sizeof(shuf_golden_setting_anwer[0]));
 			DramcDFSDirectJump(p, u1SramShuffleIdx); //fill conf SHU0 && SHU1 from SRAM SHU(0~9) while DVFS twice
 			DramcDFSDirectJump(p, u1SramShuffleIdx);
 
@@ -837,11 +837,11 @@ DRAM_STATUS_T CheckGoldenSetting(DRAMC_CTX_T *p)
 	}
 	else
 	{
-		mcSHOW_DBG_MSG(("CONF SHU0, DDR[%d]\n", p->frequency * 2));
+		msg("CONF SHU0, DDR[%d]\n", p->frequency * 2);
 		eStatus |= CheckGoldenField(p, shuf_golden_setting_anwer, sizeof(shuf_golden_setting_anwer));
 	}
 
-	mcSHOW_DBG_MSG(("Golden setting check[End]\n"));
+	msg("Golden setting check[End]\n");
 
 	vSetPHY2ChannelMapping(p, backup_channel);
 	return eStatus;
@@ -922,7 +922,7 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
 
 	u4TimeCnt = TIME_OUT_CNT;
 
-	mcSHOW_DBG_MSG(("[EnterSelfRefresh] %s\n", ((op == 1) ? "enter" : "exit")));
+	msg("[EnterSelfRefresh] %s\n", (op == 1) ? "enter" : "exit");
 
 	if (op == 1) // enter self refresh
 	{
@@ -936,7 +936,7 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
 		uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
 		while ((uiTemp == 0) && (u4TimeCnt > 0))
 		{
-			mcSHOW_DBG_MSG2(("Still not enter self refresh(%d)\n", u4TimeCnt));
+			msg2("Still not enter self refresh(%d)\n", u4TimeCnt);
 			mcDELAY_US(1);
 			uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
 			u4TimeCnt --;
@@ -950,7 +950,7 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
 		uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
 		while ((uiTemp != 0) && (u4TimeCnt > 0))
 		{
-			mcSHOW_DBG_MSG2(("Still not exit self refresh(%d)\n", u4TimeCnt));
+			msg2("Still not exit self refresh(%d)\n", u4TimeCnt);
 			mcDELAY_US(1);
 			uiTemp = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_SREF_STATE);
 			u4TimeCnt--;
@@ -959,11 +959,11 @@ void DramcEnterSelfRefresh(DRAMC_CTX_T *p, U8 op)
 
    if (u4TimeCnt == 0)
    {
-		mcSHOW_DBG_MSG(("Self refresh fail\n"));
+		msg("Self refresh fail\n");
    }
    else
    {
-		mcSHOW_DBG_MSG(("Self refresh done\n"));
+		msg("Self refresh done\n");
    }
 }
 #endif
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c
index 34f3f57d68..cd897ed917 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c
@@ -157,7 +157,7 @@ static void Set_DRAM_Pinmux_Sel(DRAMC_CTX_T *p)
 #endif
 		p->DRAMPinmux = PINMUX_EMCP;
 
-	mcSHOW_DBG_MSG(("[Set_DRAM_Pinmux_Sel] DRAMPinmux = %d\n", p->DRAMPinmux));
+	msg("[Set_DRAM_Pinmux_Sel] DRAMPinmux = %d\n", p->DRAMPinmux);
 
 	memcpy(&uiLPDDR4_MRR_Mapping_POP, uiLPDDR4_MRR_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_MRR_Mapping_POP));
 	memcpy(&uiLPDDR4_O1_Mapping_POP, uiLPDDR4_O1_DRAM_Pinmux[p->DRAMPinmux], sizeof(uiLPDDR4_O1_Mapping_POP));
@@ -276,7 +276,7 @@ static void SetRankInfoToConf(DRAMC_CTX_T *p)
 
 	vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, u4value, SA_RESERVE_SINGLE_RANK);
 
-	mcSHOW_JV_LOG_MSG(("Rank info: %d emi_setting_index: %d CONA[0x%x]\n", u4value, emi_setting_index, emi_set->EMI_CONA_VAL));
+	jv_msg("Rank info: %d emi_setting_index: %d CONA[0x%x]\n", u4value, emi_setting_index, emi_set->EMI_CONA_VAL);
 #endif
 	return;
 }
@@ -323,7 +323,7 @@ void UpdateDFSTbltoDDR3200(DRAMC_CTX_T *p)
 	#if __ETT__
 	UpdateEttDFVSTbltoDDR3200(p, u2HighestFreq); //@Darren, Update for DDR3200 ETT DVFS stress
 	#endif
-	mcSHOW_DBG_MSG(("[UpdateDFSTbltoDDR3200] Get Highest Freq is %d\n", u2HighestFreq));
+	msg("[UpdateDFSTbltoDDR3200] Get Highest Freq is %d\n", u2HighestFreq);
 #endif
 }
 
@@ -478,7 +478,7 @@ void DramcPowerOnSequence(DRAMC_CTX_T *p)
 	//// Enable  HW MIOCK control to make CLK dynamic
 	vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_TCKFIXON);
 	vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 0, DRAMC_PD_CTRL_APHYCKCG_FIXOFF);
-	mcSHOW_DBG_MSG3(("APPLY_LP4_POWER_INIT_SEQUENCE\n"));
+	msg3("APPLY_LP4_POWER_INIT_SEQUENCE\n");
 	}
 	#endif
 }
@@ -508,10 +508,10 @@ DRAM_STATUS_T DramcModeRegInit_CATerm(DRAMC_CTX_T *p, U8 bWorkAround)
 	{
 		vSetRank(p, u1RankIdx);
 
-		mcSHOW_DBG_MSG(("[DramcModeRegInit_CATerm] CH%u RK%u bWorkAround=%d\n", u1ChannelIdx, u1RankIdx, bWorkAround));
+		msg("[DramcModeRegInit_CATerm] CH%u RK%u bWorkAround=%d\n", u1ChannelIdx, u1RankIdx, bWorkAround);
 		/* FSP_1: 1. For term freqs   2. Assumes "data rate >= DDR2667" are terminated */
 		#if MRW_CHECK_ONLY
-		mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+		mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 		#endif
 		DramcMRWriteFldAlign(p, 13, 0, MR13_FSP_OP, TO_MR);
 		DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR);
@@ -654,8 +654,8 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p)
 			u1nWR = 30;
 		}
 
-		mcSHOW_DBG_MSG(("nWR fixed to %d\n", u1nWR));
-		mcDUMP_REG_MSG(("nWR fixed to %d\n", u1nWR));
+		msg("nWR fixed to %d\n", u1nWR);
+		reg_msg("nWR fixed to %d\n", u1nWR);
 	}
 
 #ifndef DUMP_INIT_RG_LOG_TO_DE
@@ -681,13 +681,13 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p)
 		{
 			vSetRank(p, u4RankIdx);
 
-			mcSHOW_DBG_MSG(("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx));
-			mcDUMP_REG_MSG(("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx));
+			msg("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx);
+			reg_msg("[ModeRegInit_LP4] CH%u RK%u\n", u1ChannelIdx, u4RankIdx);
 		#if VENDER_JV_LOG
-			mcSHOW_JV_LOG_MSG(("\n[ModeRegInit_LP4] CH%u RK%d\n", u1ChannelIdx, u4RankIdx));
+			jv_msg("\n[ModeRegInit_LP4] CH%u RK%d\n", u1ChannelIdx, u4RankIdx);
 		#endif
 		#if MRW_CHECK_ONLY
-			mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+			mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 		#endif
 
 			//vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MRS), u4RankIdx, MRS_MRSRK);
@@ -722,9 +722,9 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p)
 			{
 				/* FSP_0: 1. For un-term freqs	 2. Assumes "data rate < DDR2667" are un-term */
 				u1MRFsp = FSP_0;
-				mcSHOW_DBG_MSG3(("\tFsp%d\n", u1MRFsp));
+				msg3("\tFsp%d\n", u1MRFsp);
 			#if VENDER_JV_LOG
-				mcSHOW_JV_LOG_MSG(("\tFsp%d\n", u1MRFsp));
+				jv_msg("\tFsp%d\n", u1MRFsp);
 			#endif
 
 				u1MR13Value[u4RankIdx] = 0;
@@ -796,8 +796,8 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p)
 				DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR14 VREF-DQ
 
 			#if CALIBRATION_SPEED_UP_DEBUG
-				mcSHOW_DBG_MSG(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
-				mcSHOW_DBG_MSG(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp,u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
+				msg("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f));
+				msg("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp,u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f));
 			#endif
 
 				//MR3 set write-DBI and read-DBI (Disabled during calibration, enabled after K)
@@ -821,9 +821,9 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p)
 			{
 				/* FSP_1: 1. For term freqs   2. Assumes "data rate >= DDR2667" are terminated */
 				u1MRFsp = FSP_1;
-				mcSHOW_DBG_MSG3(("\tFsp%d\n", u1MRFsp));
+				msg3("\tFsp%d\n", u1MRFsp);
 			#if VENDER_JV_LOG
-				mcSHOW_JV_LOG_MSG(("\tFsp%d\n", u1MRFsp));
+				jv_msg("\tFsp%d\n", u1MRFsp);
 			#endif
 
 				DramcMRWriteFldAlign(p, 13, 1, MR13_FSP_WR, TO_MR);
@@ -922,8 +922,8 @@ DRAM_STATUS_T DramcModeRegInit_LP4(DRAMC_CTX_T *p)
 				DramcModeRegWriteByRank(p, u4RankIdx, 14, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]); //MR14 VREF-DQ
 
 			#if CALIBRATION_SPEED_UP_DEBUG
-				mcSHOW_DBG_MSG(("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
-				mcSHOW_DBG_MSG(("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f)));
+				msg("CBT Vref Init: CH%d Rank%d FSP%d, Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR12Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f));
+				msg("TX Vref Init: CH%d Rank%d FSP%d, TX Range %d Vref %d\n\n",p->channel, p->rank, u1MRFsp, u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp]>>6, (u1MR14Value[u1ChannelIdx][u4RankIdx][u1MRFsp] & 0x3f));
 			#endif
 
 				//MR3 set write-DBI and read-DBI (Disabled during calibration, enabled after K)
@@ -1775,30 +1775,30 @@ static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p)
 	{
 		if(p->frequency>=2133)	//Term
 		{
-			mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_4266 \n"));
+			msg("sv_algorithm_assistance_LP4_4266 \n");
 			sv_algorithm_assistance_LP4_4266(p);
 		}
 		else if(p->frequency>=1333)  //Term
 		{
-			mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_3733 \n"));
+			msg("sv_algorithm_assistance_LP4_3733 \n");
 			sv_algorithm_assistance_LP4_3733(p);
 		}
 		else if(p->frequency>400) //Unterm
 		{
-			mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_1600 \n"));
+			msg("sv_algorithm_assistance_LP4_1600 \n");
 			sv_algorithm_assistance_LP4_1600(p);
 		}
 		else /*if(p->frequency==400)*/	//DDR800 Semi-Open
 		{
-			//mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP4_1600 \n"));
+			//msg("CInit_golden_mini_freq_related_vseq_LP4_1600 \n");
 			//CInit_golden_mini_freq_related_vseq_LP4_1600(p);
 			//CInit_golden_mini_freq_related_vseq_LP4_1600_SHU1(DramcConfig);
-			mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_800 \n"));
+			msg("sv_algorithm_assistance_LP4_800 \n");
 			sv_algorithm_assistance_LP4_800(p);
 		}
 		/*else //DDR250 Open Loop (DV random seed not ready)
 		{
-			mcSHOW_DBG_MSG(("sv_algorithm_assistance_LP4_250 \n"));
+			msg("sv_algorithm_assistance_LP4_250 \n");
 			sv_algorithm_assistance_LP4_250(p);
 		}*/
 	}
@@ -1807,17 +1807,17 @@ static void SV_BroadcastOn_DramcInit(DRAMC_CTX_T *p)
 	{
 		if(p->freq_sel==LP5_DDR4266)
 		{
-			mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP5_4266 \n"));
+			msg("CInit_golden_mini_freq_related_vseq_LP5_4266 \n");
 			CInit_golden_mini_freq_related_vseq_LP5_4266(p);
 		}
 		else if(p->freq_sel==LP5_DDR5500)
 		{
-			mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP5_5500 \n"));
+			msg("CInit_golden_mini_freq_related_vseq_LP5_5500 \n");
 			CInit_golden_mini_freq_related_vseq_LP5_5500(p);
 		}
 		else
 		{
-			mcSHOW_DBG_MSG(("CInit_golden_mini_freq_related_vseq_LP5_3200 \n"));
+			msg("CInit_golden_mini_freq_related_vseq_LP5_3200 \n");
 			CInit_golden_mini_freq_related_vseq_LP5_3200(p);
 			CInit_golden_mini_freq_related_vseq_LP5_3200_SHU1(p);
 		}
@@ -1844,11 +1844,11 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
 #ifdef FOR_HQA_REPORT_USED
 	if (gHQALog_flag==1)
 	{
-		mcSHOW_DBG_MSG(("[HQA] Log parsing, "));
-		mcSHOW_DBG_MSG(("\tDram Data rate = ")); HQA_LOG_Print_Freq_String(p); mcSHOW_DBG_MSG(("\n"));
+		msg("[HQA] Log parsing, ");
+		msg("\tDram Data rate = "); HQA_LOG_Print_Freq_String(p); msg("\n");
 	}
 #endif
-	mcSHOW_DBG_MSG(("MEM_TYPE=%d, freq_sel=%d\n", MEM_TYPE, p->freq_sel));
+	msg("MEM_TYPE=%d, freq_sel=%d\n", MEM_TYPE, p->freq_sel);
 	SV_BroadcastOn_DramcInit(p); // @Darren, Broadcast Off after SV_BroadcastOn_DramcInit done
 	#if PRINT_CALIBRATION_SUMMARY
 	//default set DRAM status = NO K
@@ -1886,7 +1886,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
 
 	else if(p->freq_sel==LP4_DDR1600)
 	{
-		mcSHOW_DBG_MSG(("BYPASS CALIBRATION LP4 1600 \n"));
+		msg("BYPASS CALIBRATION LP4 1600 \n");
 		Apply_LP4_1600_Calibraton_Result(p);
 	}
 	#endif
@@ -1899,7 +1899,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
 	#endif
 	U8 dram_cbt_mode;
 
-	mcSHOW_DBG_MSG(("\n[DramcInit]\n"));
+	msg("\n[DramcInit]\n");
 
 	vSetPHY2ChannelMapping(p, CHANNEL_A);
 
@@ -1942,7 +1942,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
 			break;
 		default:
 			dram_t = 0;
-			mcSHOW_ERR_MSG(("Incorrect DRAM Type!\n"));
+			err("Incorrect DRAM Type!\n");
 			break;
 	}
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_ARBCTL), dram_t, ARBCTL_RSV_DRAM_TYPE);
@@ -1967,7 +1967,7 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
 	vSetPHY2ChannelMapping(p, save_ch);
 #endif
 
-	mcSHOW_DBG_MSG3(("[DramcInit] Done\n"));
+	msg3("[DramcInit] Done\n");
 #endif//__A60868_TO_BE_PORTING__
 	return DRAM_OK;
 }
@@ -1976,10 +1976,10 @@ DRAM_STATUS_T DramcInit(DRAMC_CTX_T *p)
 void SetCKE2RankIndependent(DRAMC_CTX_T *p)
 {
 	#if ENABLE_TMRRI_NEW_MODE//Newly added CKE control mode API
-	mcSHOW_DBG_MSG(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON\n"));
+	msg("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON\n");
 	vCKERankCtrl(p, CKE_RANK_INDEPENDENT);
 	#else //Legacy individual CKE control register settings
-	mcSHOW_DBG_MSG(("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: OFF\n"));
+	msg("SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: OFF\n");
 	vCKERankCtrl(p, CKE_RANK_DEPENDENT);
 	#endif
 }
@@ -2069,7 +2069,7 @@ void SetMr13VrcgToNormalOperation(DRAMC_CTX_T *p)
 	U8 u1RankIdx = 0;
 
 #if MRW_CHECK_ONLY
-	mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+	mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
 
 
@@ -2096,7 +2096,7 @@ static void DramcShuTrackingDcmEnBySRAM(DRAMC_CTX_T *p)
 	U32 u4DDRPhyShuOffset = 0;
 
 	ShuRGAccessIdxBak = p->ShuRGAccessIdx;
-	mcSHOW_DBG_MSG(("\n==[DramcShuTrackingDcmEnBySRAM]==\n"));
+	msg("\n==[DramcShuTrackingDcmEnBySRAM]==\n");
 	for (u1ShuffleIdx = 0; u1ShuffleIdx <= 1; u1ShuffleIdx++) //fill SHU1 of conf while (u1ShuffleIdx==DRAM_DFS_SRAM_MAX)
 	{
 		//Aceess DMA SRAM by APB bus use debug mode by conf SHU3
@@ -2215,17 +2215,17 @@ void DramcEnablePerBankRefresh(DRAMC_CTX_T *p, bool en)
 
 	#if PER_BANK_REFRESH_USE_MODE==0
 			vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); //Original mode
-			mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Original Mode\n"));
+			msg("\tPER_BANK_REFRESH: Original Mode\n");
 	#endif
 
 	#if PER_BANK_REFRESH_USE_MODE==1
 			vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(0, REFCTRL0_KEEP_PBREF) | P_Fld(1, REFCTRL0_KEEP_PBREF_OPT)); //Hybrid mode
-			mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Hybrid Mode\n"));
+			msg("\tPER_BANK_REFRESH: Hybrid Mode\n");
 	#endif
 
 	#if PER_BANK_REFRESH_USE_MODE==2
 			vIO32WriteFldMulti_All(DRAMC_REG_REFCTRL0, P_Fld(1, REFCTRL0_KEEP_PBREF) | P_Fld(0, REFCTRL0_KEEP_PBREF_OPT)); //Always per-bank mode
-			mcSHOW_DBG_MSG(("\tPER_BANK_REFRESH: Always Per-Bank Mode\n"));
+			msg("\tPER_BANK_REFRESH: Always Per-Bank Mode\n");
 	#endif
 
 		vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 1, REFCTRL1_REFPB2AB_IGZQCS);
@@ -2302,31 +2302,31 @@ static void SwitchHMR4(DRAMC_CTX_T *p, bool en)
 #if 0	// Reading HMR4 repeatedly for debugging
 	while(1)
 	{
-		mcSHOW_DBG_MSG(("@@ --------------------\n"));
-		mcSHOW_DBG_MSG(("@@ MISC_STATUSA_REFRESH_RATE: %d\n",
-			u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_RATE)));
-		mcSHOW_DBG_MSG(("@@ MIN: %d, MAX: %d\n",
+		msg("@@ --------------------\n");
+		msg("@@ MISC_STATUSA_REFRESH_RATE: %d\n",
+			u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_MISC_STATUSA), MISC_STATUSA_REFRESH_RATE));
+		msg("@@ MIN: %d, MAX: %d\n",
 			u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MIN_MON),
-			u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MAX_MON)));
+			u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON), HW_REFRATE_MON_REFRESH_RATE_MAX_MON));
 
 		// if HMR4_HMR4_TOG_OPT == 1
 		{
-			mcSHOW_DBG_MSG(("@@ 		MIN    MAX\n"));
-			mcSHOW_DBG_MSG(("@@ RK0_B0:  %d 	%d\n",
+			msg("@@ 		MIN    MAX\n");
+			msg("@@ RK0_B0:  %d 	%d\n",
 				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK0_B0),
-				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK0_B0)));
-			mcSHOW_DBG_MSG(("@@ RK1_B0:  %d 	%d\n",
+				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK0_B0));
+			msg("@@ RK1_B0:  %d 	%d\n",
 				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MIN_MON_RK1_B0),
-				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK1_B0)));
-			mcSHOW_DBG_MSG(("@@ RK0_B1:  %d 	%d\n",
+				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON3), HW_REFRATE_MON3_REFRESH_RATE_MAX_MON_RK1_B0));
+			msg("@@ RK0_B1:  %d 	%d\n",
 				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK0_B1),
-				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK0_B1)));
-			mcSHOW_DBG_MSG(("@@ RK1_B1:  %d 	%d\n",
+				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK0_B1));
+			msg("@@ RK1_B1:  %d 	%d\n",
 				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MIN_MON_RK1_B1),
-				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK1_B1)));
+				u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_HW_REFRATE_MON2), HW_REFRATE_MON2_REFRESH_RATE_MAX_MON_RK1_B1));
 		}
 
-		mcSHOW_DBG_MSG(("@@ Wait to measure!!\n\n"));
+		msg("@@ Wait to measure!!\n\n");
 		Sleep(500);
 	}
 #endif
@@ -2370,7 +2370,7 @@ void DramcCKEDebounce(DRAMC_CTX_T *p)
 		{
 			vSetRank(p, u1RKIdx);
 			vIO32WriteFldAlign_All(DRAMC_REG_SHURK_CKE_CTRL, u1CKE_DBECnt, SHURK_CKE_CTRL_CKE_DBE_CNT);
-			mcSHOW_DBG_MSG(("CKE Debounce cnt = %d\n", u1CKE_DBECnt));
+			msg("CKE Debounce cnt = %d\n", u1CKE_DBECnt);
 		}
 		vSetRank(p, rank_backup);
 	}
@@ -2398,16 +2398,16 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 	u1EnterRuntime = 1;
 #endif
 
-	mcSHOW_DBG_MSG(("[DramcRunTimeConfig]\n"));
+	msg("[DramcRunTimeConfig]\n");
 
 	SetDramInfoToConf(p);
 
 #if defined(DPM_CONTROL_AFTERK) && ((DRAMC_DFS_MODE%2) != 0) // for MD32 RG/PST mode
 	DPMInit(p);
-	mcSHOW_DBG_MSG(("DPM_CONTROL_AFTERK: ON\n"));
+	msg("DPM_CONTROL_AFTERK: ON\n");
 #else
-	mcSHOW_DBG_MSG(("!!! DPM_CONTROL_AFTERK: OFF\n"));
-	mcSHOW_DBG_MSG(("!!! DPM could not control APHY\n"));
+	msg("!!! DPM_CONTROL_AFTERK: OFF\n");
+	msg("!!! DPM could not control APHY\n");
 #endif
 
 #if ENABLE_PER_BANK_REFRESH
@@ -2415,9 +2415,9 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 	// enable pb-ref for current shu
 	vIO32WriteFldAlign_All(DRAMC_REG_SHU_CONF0, 0x1, SHU_CONF0_PBREFEN);
 	#endif
-	mcSHOW_DBG_MSG(("PER_BANK_REFRESH: ON\n"));
+	msg("PER_BANK_REFRESH: ON\n");
 #else
-	mcSHOW_DBG_MSG(("PER_BANK_REFRESH: OFF\n"));
+	msg("PER_BANK_REFRESH: OFF\n");
 #endif
 
 ///TODO:KIWI
@@ -2434,77 +2434,77 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 
 #if REFRESH_OVERHEAD_REDUCTION
 	vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL1, 0x1, REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA);
-	mcSHOW_DBG_MSG(("REFRESH_OVERHEAD_REDUCTION: ON\n"));
+	msg("REFRESH_OVERHEAD_REDUCTION: ON\n");
 #else
-	mcSHOW_DBG_MSG(("REFRESH_OVERHEAD_REDUCTION: OFF\n"));
+	msg("REFRESH_OVERHEAD_REDUCTION: OFF\n");
 #endif
 
 #if CMD_PICG_NEW_MODE
-	mcSHOW_DBG_MSG(("CMD_PICG_NEW_MODE: ON\n"));
+	msg("CMD_PICG_NEW_MODE: ON\n");
 #else
-	mcSHOW_DBG_MSG(("CMD_PICG_NEW_MODE: OFF\n"));
+	msg("CMD_PICG_NEW_MODE: OFF\n");
 #endif
 
 #if XRTWTW_NEW_CROSS_RK_MODE
 	if (p->support_rank_num == RANK_DUAL)
 	{
 		//ENABLE_XRTWTW_Setting(p); // @Darren, DV codes is included
-		mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: ON\n"));
+		msg("XRTWTW_NEW_MODE: ON\n");
 	}
 #else
-	mcSHOW_DBG_MSG(("XRTWTW_NEW_MODE: OFF\n"));
+	msg("XRTWTW_NEW_MODE: OFF\n");
 #endif
 
 #if XRTRTR_NEW_CROSS_RK_MODE
 	if (p->support_rank_num == RANK_DUAL)
 	{
 		//ENABLE_XRTRTR_Setting(p); // @Darren, DV codes is included
-		mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: ON\n"));
+		msg("XRTRTR_NEW_MODE: ON\n");
 	}
 #else
-	mcSHOW_DBG_MSG(("XRTRTR_NEW_MODE: OFF\n"));
+	msg("XRTRTR_NEW_MODE: OFF\n");
 #endif
 
 #if ENABLE_TX_TRACKING
-	mcSHOW_DBG_MSG(("TX_TRACKING: ON\n"));
+	msg("TX_TRACKING: ON\n");
 #else
-	mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n"));
+	msg("TX_TRACKING: OFF\n");
 #endif
 
 #if RDSEL_TRACKING_EN
-	mcSHOW_DBG_MSG(("RDSEL_TRACKING: ON\n"));
+	msg("RDSEL_TRACKING: ON\n");
 #else
-	mcSHOW_DBG_MSG(("RDSEL_TRACKING: OFF\n"));
+	msg("RDSEL_TRACKING: OFF\n");
 #endif
 
 #if TDQSCK_PRECALCULATION_FOR_DVFS
-	mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: "));
+	msg("DQS Precalculation for DVFS: ");
 	/* Maoauo: Enable DQS precalculation for LP4, disable for LP3(same as Kibo) */
 	DramcDQSPrecalculation_enable(p);
-	mcSHOW_DBG_MSG(("ON\n"));
+	msg("ON\n");
 #else
-	mcSHOW_DBG_MSG(("DQS Precalculation for DVFS: OFF\n"));
+	msg("DQS Precalculation for DVFS: OFF\n");
 #endif
 
 #if ENABLE_RX_TRACKING
 	DramcRxInputDelayTrackingInit_Common(p);
 	DramcRxInputDelayTrackingHW(p);
-	mcSHOW_DBG_MSG(("RX_TRACKING: ON\n"));
+	msg("RX_TRACKING: ON\n");
 #else
-	mcSHOW_DBG_MSG(("RX_TRACKING: OFF\n"));
+	msg("RX_TRACKING: OFF\n");
 #endif
 
 #if (ENABLE_RX_TRACKING && RX_DLY_TRACK_ONLY_FOR_DEBUG && defined(DUMMY_READ_FOR_TRACKING))
-	mcSHOW_DBG_MSG(("RX_DLY_TRACK_DBG: ON\n"));
+	msg("RX_DLY_TRACK_DBG: ON\n");
 	DramcRxDlyTrackDebug(p);
 #endif
 
 /* HW gating - Disabled by default(in preloader) to save power (DE: HJ Huang) */
 #if (defined(HW_GATING))
-	mcSHOW_DBG_MSG(("HW_GATING DBG: ON\n"));
+	msg("HW_GATING DBG: ON\n");
 	DramcHWGatingDebugOnOff(p, ENABLE);
 #else
-	mcSHOW_DBG_MSG(("HW_GATING DBG: OFF\n"));
+	msg("HW_GATING DBG: OFF\n");
 	DramcHWGatingDebugOnOff(p, DISABLE);
 #endif
 
@@ -2521,40 +2521,40 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 #elif (fcFOR_CHIP_ID == fcMargaux)
 	vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET1, 1, ZQ_SET1_ZQCALDISB);// LP3 and LP4 are different, be careful.
 #endif
-	mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: ON\n"));
+	msg("ZQCS_ENABLE_LP4: ON\n");
 #else
 	vIO32WriteFldAlign_All(DRAMC_REG_ZQ_SET1, 0, ZQ_SET1_ZQCALDISB);// LP3 and LP4 are different, be careful.
-	mcSHOW_DBG_MSG(("ZQCS_ENABLE_LP4: OFF\n"));
+	msg("ZQCS_ENABLE_LP4: OFF\n");
 #endif
 
 ///TODO:JEREMY
 #if 0
 #ifdef DUMMY_READ_FOR_DQS_GATING_RETRY
 	DummyReadForDqsGatingRetryNonShuffle(p, 1);
-	mcSHOW_DBG_MSG(("DUMMY_READ_FOR_DQS_GATING_RETRY: ON\n"));
+	msg("DUMMY_READ_FOR_DQS_GATING_RETRY: ON\n");
 #else
 	DummyReadForDqsGatingRetryNonShuffle(p, 0);
-	mcSHOW_DBG_MSG(("DUMMY_READ_FOR_DQS_GATING_RETRY: OFF\n"));
+	msg("DUMMY_READ_FOR_DQS_GATING_RETRY: OFF\n");
 #endif
 #endif
 
 #if RX_PICG_NEW_MODE
-	mcSHOW_DBG_MSG(("RX_PICG_NEW_MODE: ON\n"));
+	msg("RX_PICG_NEW_MODE: ON\n");
 #else
-	mcSHOW_DBG_MSG(("RX_PICG_NEW_MODE: OFF\n"));
+	msg("RX_PICG_NEW_MODE: OFF\n");
 #endif
 
 #if TX_PICG_NEW_MODE
 	TXPICGNewModeEnable(p);
-	mcSHOW_DBG_MSG(("TX_PICG_NEW_MODE: ON\n"));
+	msg("TX_PICG_NEW_MODE: ON\n");
 #else
-	mcSHOW_DBG_MSG(("TX_PICG_NEW_MODE: OFF\n"));
+	msg("TX_PICG_NEW_MODE: OFF\n");
 #endif
 
 #if ENABLE_RX_DCM_DPHY
-	mcSHOW_DBG_MSG(("ENABLE_RX_DCM_DPHY: ON\n"));
+	msg("ENABLE_RX_DCM_DPHY: ON\n");
 #else
-	mcSHOW_DBG_MSG(("ENABLE_RX_DCM_DPHY: OFF\n"));
+	msg("ENABLE_RX_DCM_DPHY: OFF\n");
 #endif
 
 #if (SW_CHANGE_FOR_SIMULATION == 0)
@@ -2563,7 +2563,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 	const char *str = (enable_dcm == 1)? ("ON") : ("OFF");
 //	  EnableDramcPhyDCM(p, enable_dcm);
 	EnableDramcPhyDCMNonShuffle(p, enable_dcm);
-	mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): %s\n", str));
+	msg("LOWPOWER_GOLDEN_SETTINGS(DCM): %s\n", str);
 
 	if(enable_dcm == 0)
 	{
@@ -2573,7 +2573,7 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 #else
 //	  EnableDramcPhyDCM(p, DCM_OFF);
 	EnableDramcPhyDCMNonShuffle(p, 0);
-	mcSHOW_DBG_MSG(("LOWPOWER_GOLDEN_SETTINGS(DCM): OFF\n"));
+	msg("LOWPOWER_GOLDEN_SETTINGS(DCM): OFF\n");
 
 	S0_DCMOffWA(p);//For S0 + DCM off
 #endif
@@ -2592,17 +2592,17 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 #ifdef DUMMY_READ_FOR_TRACKING
 	DramcDummyReadForTrackingEnable(p);
 #else
-	mcSHOW_DBG_MSG(("DUMMY_READ_FOR_TRACKING: OFF\n"));
+	msg("DUMMY_READ_FOR_TRACKING: OFF\n");
 #endif
 
 
 #ifdef SPM_CONTROL_AFTERK
 	DVFS_PRE_config(p);
 	TransferToSPMControl(p);
-	mcSHOW_DBG_MSG(("SPM_CONTROL_AFTERK: ON\n"));
+	msg("SPM_CONTROL_AFTERK: ON\n");
 #else
-	mcSHOW_DBG_MSG(("!!! SPM_CONTROL_AFTERK: OFF\n"));
-	mcSHOW_DBG_MSG(("!!! SPM could not control APHY\n"));
+	msg("!!! SPM_CONTROL_AFTERK: OFF\n");
+	msg("!!! SPM could not control APHY\n");
 #endif
 
 // when time profiling multi times, SW impedance tracking will fail when trakcing enable.
@@ -2612,14 +2612,14 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 	if (p->dram_type == TYPE_LPDDR4 || p->dram_type == TYPE_LPDDR4X)
 	{
 		DramcImpedanceTrackingEnable(p);
-		mcSHOW_DBG_MSG(("IMPEDANCE_TRACKING: ON\n"));
+		msg("IMPEDANCE_TRACKING: ON\n");
 
 #ifdef IMPEDANCE_HW_SAVING
 		DramcImpedanceHWSaving(p);
 #endif
 	}
 #else
-	mcSHOW_DBG_MSG(("IMPEDANCE_TRACKING: OFF\n"));
+	msg("IMPEDANCE_TRACKING: OFF\n");
 #endif
 #endif
 
@@ -2628,40 +2628,40 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 
 #ifdef TEMP_SENSOR_ENABLE
 	SwitchHMR4(p, ON);
-	mcSHOW_DBG_MSG(("TEMP_SENSOR: ON\n"));
+	msg("TEMP_SENSOR: ON\n");
 #else
 	SwitchHMR4(p, OFF);
-	mcSHOW_DBG_MSG(("TEMP_SENSOR: OFF\n"));
+	msg("TEMP_SENSOR: OFF\n");
 #endif
 
 #ifdef HW_SAVE_FOR_SR
-	mcSHOW_DBG_MSG(("HW_SAVE_FOR_SR: ON, no implementation\n"));
+	msg("HW_SAVE_FOR_SR: ON, no implementation\n");
 #else
-	mcSHOW_DBG_MSG(("HW_SAVE_FOR_SR: OFF\n"));
+	msg("HW_SAVE_FOR_SR: OFF\n");
 #endif
 
 #ifdef CLK_FREE_FUN_FOR_DRAMC_PSEL
 	ClkFreeRunForDramcPsel(p);
-	mcSHOW_DBG_MSG(("CLK_FREE_FUN_FOR_DRAMC_PSEL: ON\n"));
+	msg("CLK_FREE_FUN_FOR_DRAMC_PSEL: ON\n");
 #else
-	mcSHOW_DBG_MSG(("CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF\n"));
+	msg("CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF\n");
 #endif
 
 #if PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER
 	DramcPAImprove(p);
-	mcSHOW_DBG_MSG(("PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON\n"));
+	msg("PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON\n");
 #else
-	mcSHOW_DBG_MSG(("PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF\n"));
+	msg("PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF\n");
 #endif
 
 #if ENABLE_RODT_TRACKING
-	mcSHOW_DBG_MSG(("Read ODT Tracking: ON\n"));
+	msg("Read ODT Tracking: ON\n");
 #else
-	mcSHOW_DBG_MSG(("Read ODT Tracking: OFF\n"));
+	msg("Read ODT Tracking: OFF\n");
 #endif
 
 #if ENABLE_REFRESH_RATE_DEBOUNCE
-	mcSHOW_DBG_MSG(("Refresh Rate DeBounce: ON\n"));
+	msg("Refresh Rate DeBounce: ON\n");
 	DramcRefreshRateDeBounceEnable(p);
 #endif
 
@@ -2672,14 +2672,14 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 
 #if (CHECK_GOLDEN_SETTING == TRUE)
 	DRAM_STATUS_T stResult = CheckGoldenSetting(p);
-	mcSHOW_DBG_MSG(("End of run time ==>Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG")));
+	msg("End of run time ==>Golden setting check: %s\n", (stResult == DRAM_OK)? ("OK") : ("NG"));
 #endif
 
 #if DFS_NOQUEUE_FLUSH_WA
 	EnableDFSNoQueueFlush(p);
-	mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH: ON\n"));
+	msg("DFS_NO_QUEUE_FLUSH: ON\n");
 #else
-	mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH: OFF\n"));
+	msg("DFS_NO_QUEUE_FLUSH: OFF\n");
 #endif
 
 #if DFS_NOQUEUE_FLUSH_LATENCY_CNT
@@ -2687,36 +2687,36 @@ void DramcRunTimeConfig(DRAMC_CTX_T *p)
 	// MD32 clock is 208M
 	vIO32WriteFldMulti_All(DDRPHY_MD32_REG_SSPM_MCLK_DIV, P_Fld(0, SSPM_MCLK_DIV_MCLK_SRC)
 		| P_Fld(0, SSPM_MCLK_DIV_MCLK_DIV));
-	mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: ON\n"));
+	msg("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: ON\n");
 #else
-	mcSHOW_DBG_MSG(("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF\n"));
+	msg("DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF\n");
 #endif
 
 #if ENABLE_DFS_RUNTIME_MRW
 	DFSRuntimeFspMRW(p);
-	mcSHOW_DBG_MSG(("ENABLE_DFS_RUNTIME_MRW: ON\n"));
+	msg("ENABLE_DFS_RUNTIME_MRW: ON\n");
 #else
-	mcSHOW_DBG_MSG(("ENABLE_DFS_RUNTIME_MRW: OFF\n"));
+	msg("ENABLE_DFS_RUNTIME_MRW: OFF\n");
 #endif
 
 	//CheckRxPICGNewModeSetting(p);
 	vIO32WriteFldAlign_All(DRAMC_REG_REFCTRL0, 0x0, REFCTRL0_REFDIS); //After k, auto refresh should be enable
 
 #if DDR_RESERVE_NEW_MODE
-	mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: ON\n"));
+	msg("DDR_RESERVE_NEW_MODE: ON\n");
 	vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DDR_RESERVE, P_Fld(1, MISC_DDR_RESERVE_WDT_LITE_EN) | P_Fld(0, MISC_DDR_RESERVE_WDT_SM_CLR));
 #else
-	mcSHOW_DBG_MSG(("DDR_RESERVE_NEW_MODE: OFF\n"));
+	msg("DDR_RESERVE_NEW_MODE: OFF\n");
 	vIO32WriteFldMulti_All(DDRPHY_REG_MISC_DDR_RESERVE, P_Fld(0, MISC_DDR_RESERVE_WDT_LITE_EN) | P_Fld(1, MISC_DDR_RESERVE_WDT_SM_CLR));
 #endif
 
 #if MR_CBT_SWITCH_FREQ
-	mcSHOW_DBG_MSG(("MR_CBT_SWITCH_FREQ: ON\n"));
+	msg("MR_CBT_SWITCH_FREQ: ON\n");
 #else
-	mcSHOW_DBG_MSG(("MR_CBT_SWITCH_FREQ: OFF\n"));
+	msg("MR_CBT_SWITCH_FREQ: OFF\n");
 #endif
 
-	mcSHOW_DBG_MSG(("=========================\n"));
+	msg("=========================\n");
 }
 
 #if 0  //no use?
@@ -2726,7 +2726,7 @@ void DramcTest_DualSch_stress(DRAMC_CTX_T *p)
 	U16 u2Value = 0;
 
 #if MRW_CHECK_ONLY
-	mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+	mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
 
 	//vIO32WriteFldAlign_All(DRAMC_REG_PERFCTL0, 1, PERFCTL0_DUALSCHEN);
@@ -2739,7 +2739,7 @@ void DramcTest_DualSch_stress(DRAMC_CTX_T *p)
 		u1MR12Value[p->channel][p->rank][p->dram_fsp] = 0x14;
 		DramcModeRegWriteByRank(p, p->rank, 12, u1MR12Value[p->channel][p->rank][p->dram_fsp]);
 		DramcModeRegReadByRank(p, p->rank, 12, &u2Value);
-		//mcSHOW_DBG_MSG(("MR12 = 0x%0X\n", u1Value));
+		//msg("MR12 = 0x%0X\n", u1Value);
 	}
 }
 #endif
@@ -2759,7 +2759,7 @@ void SPMTx_Track_Retry_OnOff(DRAMC_CTX_T *p, U8 shu_level, U8 onoff)
 	{
 		if (onoff == ENABLE)
 		{
-			mcSHOW_DBG_MSG(("TX track retry: ENABLE! (DDR800 to DDR1200)\n"));
+			msg("TX track retry: ENABLE! (DDR800 to DDR1200)\n");
 			vIO32WriteFldAlign_All(DRAMC_REG_TX_RETRY_SET0, 1, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
 			mcDELAY_US(1);
 			#if TX_RETRY_CONTROL_BY_SPM
@@ -2770,7 +2770,7 @@ void SPMTx_Track_Retry_OnOff(DRAMC_CTX_T *p, U8 shu_level, U8 onoff)
 		}
 		else //DISABLE
 		{
-			mcSHOW_DBG_MSG(("TX track retry: DISABLE! (DDR800 to DDR1200)\n"));
+			msg("TX track retry: DISABLE! (DDR800 to DDR1200)\n");
 			#if TX_RETRY_CONTROL_BY_SPM
 			vIO32WriteFldAlign(DDRPHY_MD32_REG_LPIF_LOW_POWER_CFG_1, 0, LPIF_LOW_POWER_CFG_1_TX_TRACKING_RETRY_EN);
 			#else //control by DRAMC
@@ -2788,7 +2788,7 @@ void SWTx_Track_Retry_OnOff(DRAMC_CTX_T *p)
 {
 	U8 u4Response;
 
-	mcSHOW_DBG_MSG(("SW TX track retry!\n"));
+	msg("SW TX track retry!\n");
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 1, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 1, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
@@ -2796,7 +2796,7 @@ void SWTx_Track_Retry_OnOff(DRAMC_CTX_T *p)
 	{
 		u4Response = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_TX_RETRY_DONE_RESPONSE);
 		mcDELAY_US(1);	// Wait tZQCAL(min) 1us or wait next polling
-		mcSHOW_DBG_MSG3(("still wait tx retry be done\n", u4Response));
+		msg3("still wait tx retry be done\n", u4Response);
 	}while (u4Response == 0);
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_SW_EN);
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_RETRY_SET0), 0, TX_RETRY_SET0_XSR_TX_RETRY_BLOCK_ALE_MASK);
@@ -2809,7 +2809,7 @@ void DFSInitForCalibration(DRAMC_CTX_T *p)
 {
 #ifdef DDR_INIT_TIME_PROFILING
 	U32 CPU_Cycle;
-	mcSHOW_TIME_MSG(("*** Data rate %d ***\n\n", p->frequency << 1));
+	time_msg("*** Data rate %d ***\n\n", p->frequency << 1);
 
 	TimeProfileBegin();
 #endif
@@ -2837,8 +2837,8 @@ void DFSInitForCalibration(DRAMC_CTX_T *p)
 #if ENABLE_DUTY_SCAN_V2
 #ifdef DDR_INIT_TIME_PROFILING
 	CPU_Cycle = TimeProfileEnd();
-	mcSHOW_TIME_MSG(("	(1) DFSInitForCalibration() take %d ms\n\n", (CPU_Cycle / 1000) - gu4DutyCalibrationTime));
-	mcSHOW_TIME_MSG(("	(2) DramcNewDutyCalibration take %d ms\n\r", gu4DutyCalibrationTime));
+	time_msg("	(1) DFSInitForCalibration() take %d ms\n\n", (CPU_Cycle / 1000) - gu4DutyCalibrationTime);
+	time_msg("	(2) DramcNewDutyCalibration take %d ms\n\r", gu4DutyCalibrationTime);
 #endif
 #endif
 
@@ -2870,7 +2870,7 @@ void DFSInitForCalibration(DRAMC_CTX_T *p)
 
 #ifdef DDR_INIT_TIME_PROFILING
 	  CPU_Cycle=TimeProfileEnd();
-	  mcSHOW_TIME_MSG(("  (3) JMeter takes %d ms\n\r", CPU_Cycle / 1000));
+	  time_msg("  (3) JMeter takes %d ms\n\r", CPU_Cycle / 1000);
 #endif
 	}
 
@@ -2961,7 +2961,7 @@ void GetTXPICGSetting(DRAMC_CTX_T * p)
 	U16 u2COMB_TX_PICG_CNT;
 	U8 u1CHIdx, u1RankIdx, u1Rank_bak = u1GetRank(p), u1backup_CH = vGetPHY2ChannelMapping(p), u1Div_ratio;
 
-	mcSHOW_DBG_MSG(("****** GetTXPICGSetting DDR[%d] @@@\n", p->frequency * 2));
+	msg("****** GetTXPICGSetting DDR[%d] @@@\n", p->frequency * 2);
 
 	for (u1CHIdx = 0; u1CHIdx < p->support_channel_num; u1CHIdx++)
 	{
@@ -2974,9 +2974,9 @@ void GetTXPICGSetting(DRAMC_CTX_T * p)
 		u2DQS_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS0), SHU_SELPH_DQS0_TXDLY_OEN_DQS1);//m
 		u2DQS_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_SELPH_DQS1), SHU_SELPH_DQS1_DLY_OEN_DQS1);//n
 
-		mcSHOW_DBG_MSG(("CH%d\n", u1CHIdx));
-		mcSHOW_DBG_MSG(("DQS0 m=%d n=%d \n", u2DQS_OEN_2T[0], u2DQS_OEN_05T[0]));
-		mcSHOW_DBG_MSG(("DQS1 m=%d n=%d \n", u2DQS_OEN_2T[1], u2DQS_OEN_05T[1]));
+		msg("CH%d\n", u1CHIdx);
+		msg("DQS0 m=%d n=%d \n", u2DQS_OEN_2T[0], u2DQS_OEN_05T[0]);
+		msg("DQS1 m=%d n=%d \n", u2DQS_OEN_2T[1], u2DQS_OEN_05T[1]);
 
 
 
@@ -2984,14 +2984,14 @@ void GetTXPICGSetting(DRAMC_CTX_T * p)
 		u2COMB_TX_SEL[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1);
 		u2COMB_TX_PICG_CNT = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_APHY_TX_PICG_CTRL), SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_PICG_CNT);
 
-		mcSHOW_DBG_MSG(("TX_DQS_SEL_P0 %d \n", u2COMB_TX_SEL[0]));
-		mcSHOW_DBG_MSG(("TX_DQS_SEL_P1 %d \n", u2COMB_TX_SEL[1]));
-		mcSHOW_DBG_MSG(("COMB_TX_PICG_CNT %d \n", u2COMB_TX_PICG_CNT));
+		msg("TX_DQS_SEL_P0 %d \n", u2COMB_TX_SEL[0]);
+		msg("TX_DQS_SEL_P1 %d \n", u2COMB_TX_SEL[1]);
+		msg("COMB_TX_PICG_CNT %d \n", u2COMB_TX_PICG_CNT);
 
 		//Set TX RK0 and RK1 DQ PICG
 		for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
 		{
-			mcSHOW_DBG_MSG(("Rank%d\n", u1RankIdx));
+			msg("Rank%d\n", u1RankIdx);
 
 			vSetRank(p, u1RankIdx);
 			//DQ0
@@ -3001,14 +3001,14 @@ void GetTXPICGSetting(DRAMC_CTX_T * p)
 			u2DQ_OEN_2T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), SHURK_SELPH_DQ0_TXDLY_OEN_DQ1);//p
 			u2DQ_OEN_05T[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ2), SHURK_SELPH_DQ2_DLY_OEN_DQ1);//q
 
-			mcSHOW_DBG_MSG(("DQ0 p=%d q=%d \n", u2DQ_OEN_2T[0], u2DQ_OEN_05T[0]));
-			mcSHOW_DBG_MSG(("DQ1 p=%d q=%d \n", u2DQ_OEN_2T[1], u2DQ_OEN_05T[1]));
+			msg("DQ0 p=%d q=%d \n", u2DQ_OEN_2T[0], u2DQ_OEN_05T[0]);
+			msg("DQ1 p=%d q=%d \n", u2DQ_OEN_2T[1], u2DQ_OEN_05T[1]);
 
 			u2COMB_TX_SEL[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0);
 			u2COMB_TX_SEL[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1);
 
-			mcSHOW_DBG_MSG(("TX_DQ_RK_SEL_P0 %d \n", u2COMB_TX_SEL[0]));
-			mcSHOW_DBG_MSG(("TX_DQ_RK_SEL_P1 %d \n", u2COMB_TX_SEL[1]));
+			msg("TX_DQ_RK_SEL_P0 %d \n", u2COMB_TX_SEL[0]);
+			msg("TX_DQ_RK_SEL_P1 %d \n", u2COMB_TX_SEL[1]);
 		}
 		vSetRank(p, u1Rank_bak);
 	}
@@ -3584,7 +3584,7 @@ unsigned int DDRPhyFreqMeter(void)
 
 	// abist_clk29: AD_MPLL_CK
 	frq_result = FMeter(ABIST_FMETER, 29) ;
-	mcSHOW_DBG_MSG(("AD_MPLL_CK FREQ=%d\n", frq_result));
+	msg("AD_MPLL_CK FREQ=%d\n", frq_result);
 	/*TINFO="AD_MPLL_CK FREQ=%d\n", frq_result*/
 
 	// abist_clk40: DA_MPLL_52M_DIV_CK
@@ -3595,14 +3595,14 @@ unsigned int DDRPhyFreqMeter(void)
 	{
 		// abist_clk31: AD_RCLRPLL_DIV4_CK_ch02
 		//frq_result = FMeter(ABIST_FMETER, 31) ;
-		mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result));
+		msg("AD_RCLRPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result);
 		/*TINFO="AD_RCLRPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result*/
 	}
 	else
 	{
 		// abist_clk33: AD_RPHYRPLL_DIV4_CK_ch02
 		frq_result = FMeter(ABIST_FMETER, 33) ;
-		mcSHOW_DBG_MSG(("AD_RPHYPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result));
+		msg("AD_RPHYPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result);
 		/*TINFO="AD_RPHYPLL_DIV4_CK_ch02 FREQ=%d\n", frq_result*/
 	}
 	#endif
@@ -3612,7 +3612,7 @@ unsigned int DDRPhyFreqMeter(void)
 
 	// abistgen_clk44: fmem_ck_aft_dcm_ch0 (DRAMC CHA's clock after idle mask)
 	before_value = FMeter(ABIST_FMETER, 44);
-	mcSHOW_DBG_MSG(("fmem_ck_aft_dcm_ch0 FREQ=%d\n", before_value));
+	msg("fmem_ck_aft_dcm_ch0 FREQ=%d\n", before_value);
 	/*TINFO="fmem_ck_aft_dcm_ch0 FREQ=%d\n", after_value*/
 
 #if (fcFOR_CHIP_ID == fcMargaux)
@@ -3623,7 +3623,7 @@ unsigned int DDRPhyFreqMeter(void)
 		DRV_WriteReg32	(Channel_B_DDRPHY_AO_BASE_ADDRESS + 0x504  , reg0 | (1 << 11));
 	// abistgen_clk45: fmem_ck_aft_dcm_ch1 (DRAMC CHB's clock after idle mask)
 	after_value = FMeter(ABIST_FMETER, 45);
-	mcSHOW_DBG_MSG(("fmem_ck_aft_dcm_ch1 FREQ=%d\n", after_value));
+	msg("fmem_ck_aft_dcm_ch1 FREQ=%d\n", after_value);
 	}
 	/*TINFO="fmem_ck_aft_dcm_ch1 FREQ=%d\n", after_value*/
 
@@ -3645,14 +3645,14 @@ unsigned int DDRPhyFreqMeter(void)
 	{
 		// abist_clk32: AD_RCLRPLL_DIV4_CK_ch13
 		//frq_result = FMeter(ABIST_FMETER, 32) ;
-		mcSHOW_DBG_MSG(("AD_RCLRPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result));
+		msg("AD_RCLRPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result);
 		/*TINFO="AD_RCLRPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result*/
 	}
 	else
 	{
 		// abist_clk34: AD_RPHYRPLL_DIV4_CK_ch13
 		frq_result = FMeter(ABIST_FMETER, 34) ;
-		mcSHOW_DBG_MSG(("AD_RPHYPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result));
+		msg("AD_RPHYPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result);
 		/*TINFO="AD_RPHYPLL_DIV4_CK_ch13 FREQ=%d\n", frq_result*/
 	}
 	#endif
@@ -3664,12 +3664,12 @@ unsigned int DDRPhyFreqMeter(void)
 
 	// abistgen_clk46: fmem_ck_aft_dcm_ch2 (DRAMC CHC's clock after idle mask)
 	before_value = FMeter(ABIST_FMETER, 46);
-	mcSHOW_DBG_MSG(("fmem_ck_aft_dcm_ch2 FREQ=%d\n", before_value));
+	msg("fmem_ck_aft_dcm_ch2 FREQ=%d\n", before_value);
 	/*TINFO="fmem_ck_aft_dcm_ch2 FREQ=%d\n", after_value*/
 
 	// abistgen_clk47: fmem_ck_aft_dcm_ch3 (DRAMC CHC's clock after idle mask)
 	after_value = FMeter(ABIST_FMETER, 47);
-	mcSHOW_DBG_MSG(("fmem_ck_aft_dcm_ch3 FREQ=%d\n", after_value));
+	msg("fmem_ck_aft_dcm_ch3 FREQ=%d\n", after_value);
 	/*TINFO="fmem_ck_aft_dcm_ch3 FREQ=%d\n", after_value*/
 
 	reg0 = DRV_Reg32(Channel_C_DDRPHY_AO_BASE_ADDRESS + 0x70c) ;
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c
index 1540770072..2e1c804648 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c
@@ -236,7 +236,7 @@ void Fast_K_CheckResult(DRAMC_CTX_T *p, U8 ucCalType)
 		debug_cnt[0] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B0));
 		debug_cnt[1] = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_CAL_DQSG_CNT_B1));
 
-		//mcSHOW_DBG_MSG((" 0x%X  ",u4DebugCnt))
+		//msg(" 0x%X  ",u4DebugCnt)
 		if (debug_cnt[0]==0x4646 && debug_cnt[1]==0x4646)
 			CheckResult=0;
 
@@ -247,13 +247,13 @@ void Fast_K_CheckResult(DRAMC_CTX_T *p, U8 ucCalType)
 
 	if ((FastK_Check_flag==1)&&(CheckResult==0))
 	{
-		//mcSHOW_DBG_MSG((" [FAST K CHECK]->PASS\n"))
+		//msg(" [FAST K CHECK]->PASS\n")
 		*Pointer_FastKResult &= (~(1<<ucCalType)); // result PASS
 		*Pointer_FastKExecute |= (1<<ucCalType);; // Excuted
 	}
 	else if ((FastK_Check_flag==1)&&(CheckResult !=0))
 	{
-		//mcSHOW_DBG_MSG((" [FAST K CHECK]->FAIL\n"))
+		//msg(" [FAST K CHECK]->FAIL\n")
 		*Pointer_FastKResult |= (1<<ucCalType); // result FAIL
 		*Pointer_FastKExecute |= (1<<ucCalType);; // Excuted
 	}
@@ -283,11 +283,11 @@ void vPrintCalibrationResult(DRAMC_CTX_T *p)
 	U8 ucCalResult, ucCalExecute;
 	U8 u1CalibrationFail;
 
-	mcSHOW_DBG_MSG(("\n\n[Calibration Summary] %d Mbps\n", p->frequency * 2));
+	msg("\n\n[Calibration Summary] %d Mbps\n", p->frequency * 2);
 
 	//for(ucFreqIdx=0; ucFreqIdx<DRAM_DFS_SHUFFLE_MAX; ucFreqIdx++)
 	{
-		//mcSHOW_DBG_MSG(("==Freqency = %d==\n", get_FreqTbl_by_shuffleIndex(p,ucFreqIdx)->frequency));
+		//msg("==Freqency = %d==\n", get_FreqTbl_by_shuffleIndex(p,ucFreqIdx)->frequency);
 		for(ucCHIdx=0; ucCHIdx<p->support_channel_num; ucCHIdx++)
 		{
 			for(ucRankIdx=0; ucRankIdx<p->support_rank_num; ucRankIdx++)
@@ -295,8 +295,8 @@ void vPrintCalibrationResult(DRAMC_CTX_T *p)
 				u1CalibrationFail =0;
 				ucCalExecute_All = p->aru4CalExecuteFlag[ucCHIdx][ucRankIdx];
 				ucCalResult_All = p->aru4CalResultFlag[ucCHIdx][ucRankIdx];
-				mcSHOW_DBG_MSG(("CH %d, Rank %d\n", ucCHIdx, ucRankIdx));
-				//mcSHOW_DBG_MSG(("[vPrintCalibrationResult] Channel = %d, Rank= %d, Freq.= %d, (ucCalExecute_All 0x%x, ucCalResult_All 0x%x)\n", ucCHIdx, ucRankIdx, ucFreqIdx, ucCalExecute_All, ucCalResult_All));
+				msg("CH %d, Rank %d\n", ucCHIdx, ucRankIdx);
+				//msg("[vPrintCalibrationResult] Channel = %d, Rank= %d, Freq.= %d, (ucCalExecute_All 0x%x, ucCalResult_All 0x%x)\n", ucCHIdx, ucRankIdx, ucFreqIdx, ucCalExecute_All, ucCalResult_All);
 
 				for(ucCalIdx =0; ucCalIdx<DRAM_CALIBRATION_MAX; ucCalIdx++)
 				{
@@ -312,39 +312,39 @@ void vPrintCalibrationResult(DRAMC_CTX_T *p)
 						}
 
 					#if PRINT_CALIBRATION_SUMMARY_DETAIL
-					mcSHOW_DBG_MSG(("%s: ", szCalibStatusName[ucCalIdx]))
+					msg("%s: ", szCalibStatusName[ucCalIdx])
 					if(ucCalExecute==1 && ucCalResult ==1) // excuted and fail
 					{
 						u1CalibrationFail =1;
-						mcSHOW_DBG_MSG(("%s\n", "@_@FAIL@_@"))
+						msg("%s\n", "@_@FAIL@_@")
 					}
 					else if (ucCalExecute==1 && ucCalResult ==0) // DRAM_OK
 					{
-						mcSHOW_DBG_MSG(("%s\n", "PASS"))
+						msg("%s\n", "PASS")
 					}
 					else if (ucCalExecute==0 && ucCalResult ==0) // DRAM_FAST K
 					{
-						mcSHOW_DBG_MSG(("%s\n", "FAST K"))
+						msg("%s\n", "FAST K")
 					}
 					else //DRAM_NO K
 					{
-						mcSHOW_DBG_MSG(("%s\n", "NO K"))
+						msg("%s\n", "NO K")
 					}
 
 					#else
 					if(ucCalExecute==1 && ucCalResult ==1) // excuted and fail
 					{
 						u1CalibrationFail =1;
-						mcSHOW_DBG_MSG(("%s: %s\n", szCalibStatusName[ucCalIdx],"@_@FAIL@_@"))
+						msg("%s: %s\n", szCalibStatusName[ucCalIdx],"@_@FAIL@_@")
 					}
 					#endif
 				}
 
 				if(u1CalibrationFail ==0)
 				{
-					mcSHOW_DBG_MSG(("All Pass.\n"));
+					msg("All Pass.\n");
 				}
-				mcSHOW_DBG_MSG(("\n"));
+				msg("\n");
 			}
 		}
 	}
@@ -373,12 +373,12 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p)
 {
 	U8 u1CHIdx, u1RankIdx, u1CAIdx, u1ByteIdx, u1ByteIdx_DQ, u1BitIdx, u1BitIdx_DQ, u1FreqRegionIdx, u1ImpIdx;
 	U8 u1PinError=0;
-	mcSHOW_DBG_MSG(("\n\n[Pin Info Summary] Freqency %d\n", p->frequency));
+	msg("\n\n[Pin Info Summary] Freqency %d\n", p->frequency);
 	for (u1FreqRegionIdx=0;u1FreqRegionIdx<2/*IMP_VREF_MAX*/;u1FreqRegionIdx++)
 	{
 		for (u1ImpIdx=0;u1ImpIdx<IMP_DRV_MAX;u1ImpIdx++)
 		{
-			mcSHOW_DBG_MSG(("IMP %s type:%s %s\n", u1FreqRegionIdx?"Region1":"Region0", print_Impedence_LOG_type(u1ImpIdx), ((PINInfo_flashtool.IMP_ERR_FLAG>>(u1FreqRegionIdx*4+u1ImpIdx)&0x1)?"ERROR":"PASS")));
+			msg("IMP %s type:%s %s\n", u1FreqRegionIdx?"Region1":"Region0", print_Impedence_LOG_type(u1ImpIdx), (PINInfo_flashtool.IMP_ERR_FLAG>>(u1FreqRegionIdx*4+u1ImpIdx)&0x1)?"ERROR":"PASS");
 		}
 	}
 	{
@@ -386,7 +386,7 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p)
 		{
 			for(u1RankIdx=0; u1RankIdx<p->support_rank_num; u1RankIdx++)
 			{
-				mcSHOW_DBG_MSG(("CH %d, Rank %d\n", u1CHIdx, u1RankIdx));
+				msg("CH %d, Rank %d\n", u1CHIdx, u1RankIdx);
 				for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++)
 				{
 					#if 1//Transfer to Percentage
@@ -399,11 +399,11 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p)
 						PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx] |= (1<<u1CAIdx);
 						PINInfo_flashtool.TOTAL_ERR |= (0x1<<(u1CHIdx*4+u1RankIdx*2));
 					}
-					mcSHOW_DBG_MSG(("CA %d: %s ", u1CAIdx, ((PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx]>>u1CAIdx)&0x1)?"ERROR":"PASS"));
+					msg("CA %d: %s ", u1CAIdx, (PINInfo_flashtool.CA_ERR_FLAG[u1CHIdx][u1RankIdx]>>u1CAIdx) & 0x1 ? "ERROR" : "PASS");
 					#if PRINT_WIN_SIZE
-					mcSHOW_DBG_MSG(("(WIN_SIZE: %d %% )", (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx])));
+					msg("(WIN_SIZE: %d %% )", (PINInfo_flashtool.CA_WIN_SIZE[u1CHIdx][u1RankIdx][u1CAIdx]));
 					#endif
-					mcSHOW_DBG_MSG(("\n"));
+					msg("\n");
 				}
 				for (u1BitIdx =0; u1BitIdx <DQ_DATA_WIDTH_LP4; u1BitIdx++)
 				{
@@ -438,12 +438,12 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p)
 				for (u1BitIdx_DQ=0; u1BitIdx_DQ<DQ_DATA_WIDTH_LP4; u1BitIdx_DQ++)
 				{
 					u1ByteIdx_DQ = (u1BitIdx_DQ>=8?1:0);
-					mcSHOW_DBG_MSG(("DRAM DQ %d: RX %s, TX %s ", u1BitIdx_DQ, (((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS"),\
-																														(((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS")));
+					msg("DRAM DQ %d: RX %s, TX %s ", u1BitIdx_DQ, ((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0))&0x1)?"ERROR":"PASS"),\
+																														(((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx_DQ]>>(u1BitIdx_DQ-(u1ByteIdx_DQ==1?8:0)))&0x1)?"ERROR":"PASS"));
 					#if PRINT_WIN_SIZE
-					mcSHOW_DBG_MSG(("(RX WIN SIZE: %d %%, TX WIN SIZE: %d %% )", PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]], PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]]));
+					msg("(RX WIN SIZE: %d %%, TX WIN SIZE: %d %% )", PINInfo_flashtool.DQ_RX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]], PINInfo_flashtool.DQ_TX_WIN_SIZE[u1CHIdx][u1RankIdx][uiLPDDR4_O1_Mapping_POP[u1CHIdx][u1BitIdx_DQ]]);
 					#endif
-					mcSHOW_DBG_MSG(("\n"));
+					msg("\n");
 				}
 			}
 		}
@@ -452,22 +452,22 @@ void vPrintPinInfoResult(DRAMC_CTX_T *p)
 void vGetErrorTypeResult(DRAMC_CTX_T *p)
 {
 	U8 u1CHIdx, u1CHIdx_EMI, u1RankIdx, u1CAIdx, u1ByteIdx, u1BitIdx, u1FreqRegionIdx, u1ImpIdx;
-	mcSHOW_DBG_MSG(("\n[Get Pin Error Type Result]\n"));
+	msg("\n[Get Pin Error Type Result]\n");
 	if (PINInfo_flashtool.TOTAL_ERR==0 && PINInfo_flashtool.IMP_ERR_FLAG==0)//ALL PASS
 	{
-		mcSHOW_DBG_MSG(("ALL PASS\n"));
+		msg("ALL PASS\n");
 	}
 	if (PINInfo_flashtool.IMP_ERR_FLAG)
 	{
-		mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: Impedance calibration fail\n"));
-		mcSHOW_DBG_MSG(("Suspect EXTR contact issue\n"));
-		mcSHOW_DBG_MSG(("Suspect EXTR related resistor contact issue\n"));
+		msg("[CHECK RESULT] FAIL: Impedance calibration fail\n");
+		msg("Suspect EXTR contact issue\n");
+		msg("Suspect EXTR related resistor contact issue\n");
 	}
 	if ((PINInfo_flashtool.TOTAL_ERR == 0xffff) && (PINInfo_flashtool.WL_ERR_FLAG== 0xff))
 	{
-		mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: ALL calibration fail\n"));
-		mcSHOW_DBG_MSG(("Suspect RESET_N contact issue\n"));
-		mcSHOW_DBG_MSG(("Suspect DRAM Power (VDD1/VDD2/VDDQ) contact issue\n"));
+		msg("[CHECK RESULT] FAIL: ALL calibration fail\n");
+		msg("Suspect RESET_N contact issue\n");
+		msg("Suspect DRAM Power (VDD1/VDD2/VDDQ) contact issue\n");
 	}
 	else
 	{
@@ -483,12 +483,12 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p)
 				u1CHIdx_EMI = u1CHIdx;
 			if ((PINInfo_flashtool.TOTAL_ERR>>(u1CHIdx*4) & 0xf) == 0xf)
 			{
-				mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d all calibration fail\n",u1CHIdx));
-				mcSHOW_DBG_MSG(("Suspect EMI%d_CK_T contact issue\n",u1CHIdx_EMI));
-				mcSHOW_DBG_MSG(("Suspect EMI%d_CK_C contact issue\n",u1CHIdx_EMI));
+				msg("[CHECK RESULT] FAIL: CH%d all calibration fail\n",u1CHIdx);
+				msg("Suspect EMI%d_CK_T contact issue\n",u1CHIdx_EMI);
+				msg("Suspect EMI%d_CK_C contact issue\n",u1CHIdx_EMI);
 				for (u1CAIdx =0; u1CAIdx <CATRAINING_NUM_LP4; u1CAIdx++)
 				{
-					mcSHOW_DBG_MSG(("Suspect EMI%d_CA%d contact issue\n",u1CHIdx_EMI,u1CAIdx));
+					msg("Suspect EMI%d_CA%d contact issue\n",u1CHIdx_EMI,u1CAIdx);
 				}
 			}
 			else
@@ -501,9 +501,9 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p)
 						 (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_0] == 0xff) && \
 						 (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][BYTE_1] == 0xff))
 					{
-						mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d RK%d all calibration fail\n",u1CHIdx,u1RankIdx));
-						mcSHOW_DBG_MSG(("Suspect EMI%d_CKE_%d contact issue\n",u1CHIdx_EMI,u1RankIdx));
-						mcSHOW_DBG_MSG(("Suspect EMI%d_CS_%d contact issue\n",u1CHIdx_EMI,u1RankIdx));
+						msg("[CHECK RESULT] FAIL: CH%d RK%d all calibration fail\n",u1CHIdx,u1RankIdx);
+						msg("Suspect EMI%d_CKE_%d contact issue\n",u1CHIdx_EMI,u1RankIdx);
+						msg("Suspect EMI%d_CS_%d contact issue\n",u1CHIdx_EMI,u1RankIdx);
 					}
 					else
 					{
@@ -512,9 +512,9 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p)
 							if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) &&\
 									  (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff))
 							{
-								mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d RK%d Byte%d WL/Read/Write calibration fail\n",u1CHIdx,u1RankIdx,u1ByteIdx));
-								mcSHOW_DBG_MSG(("Suspect EMI%d_DQS%d_T contact issue\n",u1CHIdx_EMI,u1ByteIdx));
-								mcSHOW_DBG_MSG(("Suspect EMI%d_DQS%d_C contact issue\n",u1CHIdx_EMI,u1ByteIdx));
+								msg("[CHECK RESULT] FAIL: CH%d RK%d Byte%d WL/Read/Write calibration fail\n",u1CHIdx,u1RankIdx,u1ByteIdx);
+								msg("Suspect EMI%d_DQS%d_T contact issue\n",u1CHIdx_EMI,u1ByteIdx);
+								msg("Suspect EMI%d_DQS%d_C contact issue\n",u1CHIdx_EMI,u1ByteIdx);
 							}
 							else if (PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]&&\
 									   PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx])
@@ -524,15 +524,15 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p)
 									if (((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1)&&\
 										 ((PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx]>>u1BitIdx)&0x1))
 									{
-											mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d RK%d DRAM DQ%d Read/Write fail\n",u1CHIdx,u1RankIdx,u1ByteIdx*8+u1BitIdx));
-											mcSHOW_DBG_MSG(("Suspect EMI%d_DQ%d contact issue\n",u1CHIdx_EMI,u1ByteIdx*8+u1BitIdx));
+											msg("[CHECK RESULT] FAIL: CH%d RK%d DRAM DQ%d Read/Write fail\n",u1CHIdx,u1RankIdx,u1ByteIdx*8+u1BitIdx);
+											msg("Suspect EMI%d_DQ%d contact issue\n",u1CHIdx_EMI,u1ByteIdx*8+u1BitIdx);
 									}
 								}
 							}
 							else if((PINInfo_flashtool.DRAM_PIN_RX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff) ||\
 									  (PINInfo_flashtool.DRAM_PIN_TX_ERR_FLAG[u1CHIdx][u1RankIdx][u1ByteIdx] == 0xff))
 							{
-								mcSHOW_DBG_MSG(("[CHECK RESULT] FAIL: CH%d RK%d Byte%d Suspect other special contact or calibration issue\n",u1CHIdx_EMI,u1RankIdx,u1ByteIdx));
+								msg("[CHECK RESULT] FAIL: CH%d RK%d Byte%d Suspect other special contact or calibration issue\n",u1CHIdx_EMI,u1RankIdx,u1ByteIdx);
 							}
 						}
 					}
@@ -540,7 +540,7 @@ void vGetErrorTypeResult(DRAMC_CTX_T *p)
 			}
 		}
 	}
-	mcSHOW_DBG_MSG(("\n"));
+	msg("\n");
 	return;
 }
 #endif
@@ -1194,7 +1194,7 @@ static void set_cbt_wlev_intv_lp4(DRAMC_CTX_T *p)
 	pintv = lookup_cbt_intv(intv, ARRAY_SIZE(intv),
 			p->freq_sel, vGet_Div_Mode(p));
 	if (!pintv) {
-		mcSHOW_DBG_MSG(("not found entry!\n"));
+		msg("not found entry!\n");
 		return;
 	}
 
@@ -1289,7 +1289,7 @@ static void set_cbt_wlev_intv_lp5(DRAMC_CTX_T *p)
 
 	pintv = lookup_cbt_intv(intv, ARRAY_SIZE(intv), p->freq_sel, UNKNOWN_MODE);
 	if (!pintv) {
-		mcSHOW_DBG_MSG(("not found entry!\n"));
+		msg("not found entry!\n");
 		return;
 	}
 
@@ -1543,7 +1543,7 @@ static u8 get_mck_ck_ratio(DRAMC_CTX_T *p)
 	ratio = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_LP5_CMD),
 		SHU_LP5_CMD_LP5_CMD1TO2EN);
 
-	mcSHOW_DBG_MSG5(("LP5 MCK:CK=%s\n", ratio == 1 ? "1:1" : "1:2"));
+	msg5("LP5 MCK:CK=%s\n", ratio == 1 ? "1:1" : "1:2");
 
 	return ratio;
 }
@@ -1685,8 +1685,8 @@ static S16 adjust_ca_ui(DRAMC_CTX_T *p, U32 ca_mck,
 
 	put_ca_ui(p, ui_new);
 	put_ca_mck(p, mck_new);
-	mcSHOW_DBG_MSG5(("mck_new: 0x%x, ui_new: 0x%x, pi:%d\n",
-		mck_new, ui_new, pi));
+	msg5("mck_new: 0x%x, ui_new: 0x%x, pi:%d\n",
+		mck_new, ui_new, pi);
 
 	return pi;
 }
@@ -1778,10 +1778,10 @@ static S16 adjust_cs_ui(DRAMC_CTX_T *p, u32 cs_mck, u32 cs_ui, S16 pi_dly)
 	put_cs_ui(p, cs_ui_tmp);
 	put_cs_mck(p, cs_mck_tmp);
 
-	mcSHOW_DBG_MSG5(("csmck:%d, csui: %d, pi:%d before\n",
-			cs_mck, cs_ui, 0));
-	mcSHOW_DBG_MSG5(("csmck:%d, csui: %d, pi:%d after\n",
-			cs_mck_tmp, cs_ui_tmp, pi));
+	msg5("csmck:%d, csui: %d, pi:%d before\n",
+			cs_mck, cs_ui, 0);
+	msg5("csmck:%d, csui: %d, pi:%d after\n",
+			cs_mck_tmp, cs_ui_tmp, pi);
 
 	return pi;
 }
@@ -1937,8 +1937,8 @@ static u32 CBTDelayCACLKCompareWorkaround(DRAMC_CTX_T *p)
 
 			if (u4TimeCnt == 0)//time out
 			{
-				mcSHOW_DBG_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n"));
-				mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test
+				msg("[CBTDelayCACLKCompare] Resp fail (time out)\n");
+				mcFPRINTF(fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n");//Eddie Test
 				//return DRAM_FAIL;
 			}
 
@@ -2047,8 +2047,8 @@ static u32 new_cbt_pat_compare_workaround(DRAMC_CTX_T *p, new_cbt_pat_cfg_t *ncm
 
 			if (u4TimeCnt == 0)//time out
 			{
-				mcSHOW_DBG_MSG(("[CBTDelayCACLKCompare] Resp fail (time out)\n"));
-				mcFPRINTF((fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n"));//Eddie Test
+				msg("[CBTDelayCACLKCompare] Resp fail (time out)\n");
+				mcFPRINTF(fp_A60868, "[CBTDelayCACLKCompare] Resp fail (time out)\n");//Eddie Test
 				//return DRAM_FAIL;
 			}
 
@@ -2157,7 +2157,7 @@ static void CBTAdjustCS(DRAMC_CTX_T *p, int autok)
 
 	vSetRank(p, backup_rank);
 
-	mcSHOW_DBG_MSG(("CS Dly: %d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass));
+	msg("CS Dly: %d (%d~%d)\n", iCSFinalDelay, iFirstCSPass, iLastCSPass);
 }
 
 #if CA_PER_BIT_DELAY_CELL
@@ -2217,7 +2217,7 @@ static void CBTSetCACLKResult(DRAMC_CTX_T *p, U32 u4MCK, U32 u4UI, S8 iFinalCACL
 
 	iFinalCACLK = CATrain_CmdDelay[p->channel][p->rank];
 
-	mcSHOW_DBG_MSG(("\n[CBTSetCACLKResult] CA Dly = %d\n", iFinalCACLK));
+	msg("\n[CBTSetCACLKResult] CA Dly = %d\n", iFinalCACLK);
 
 	iFinalCACLK = adjust_ca_ui(p, u4MCK, u4UI, iFinalCACLK);
 
@@ -2250,14 +2250,14 @@ static U8 GetCBTVrefPinMuxValue_lp5(DRAMC_CTX_T *p, U8 u1VrefLevel)
 
 	for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++)
 	{
-		//mcSHOW_DBG_MSG(("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]));
+		//msg("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]);
 		if (u2Vref_org & (1 << u2VrefBit))
 		{
 			u2Vref_new |= (1 << uiLPDDR5_O1_Mapping_POP[p->channel][u2VrefBit]);
 		}
 	}
 
-	mcSHOW_DBG_MSG3(("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new));
+	msg3("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new);
 
 	if (lp5_cp[p->channel].dram_dq_b0)
 		u2Vref_new >>= 8;
@@ -2280,14 +2280,14 @@ static U8 GetCBTVrefPinMuxValue(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel)
 	u2Vref_new = 0;
 	for (u2VrefBit = 0; u2VrefBit < 8; u2VrefBit++)
 	{
-		//mcSHOW_DBG_MSG(("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]));
+		//msg("=== u2VrefBit: %d, %d\n",u2VrefBit,uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]);
 		if (u2Vref_org & (1 << u2VrefBit))
 		{
 			u2Vref_new |= (1 << uiLPDDR4_O1_Mapping_POP[p->channel][u2VrefBit]);
 		}
 	}
 
-	mcSHOW_DBG_MSG3(("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new));
+	msg3("=== u2Vref_new: 0x%x --> 0x%x\n", u2Vref_org, u2Vref_new);
 
 	if (lp4_cp[p->channel].dram_dq_b0)
 		u2Vref_new >>= 8;
@@ -2308,7 +2308,7 @@ static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 ope
 		u1VrefValue_pinmux = GetCBTVrefPinMuxValue(p, u1VrefRange, u1VrefLevel);
 
 #if !REDUCE_LOG_FOR_PRELOADER
-		mcSHOW_DBG_MSG(("\nCH_%d, RK_%d, Range=%d, VrefValue_pinmux = 0x%x\n", p->channel, p->rank, u1VrefRange, u1VrefValue_pinmux));
+		msg("\nCH_%d, RK_%d, Range=%d, VrefValue_pinmux = 0x%x\n", p->channel, p->rank, u1VrefRange, u1VrefValue_pinmux);
 #endif
 		u1MR12Value[p->channel][p->rank][operating_fsp] = ((u1VrefRange & 0x1) << 6) | u1VrefLevel;
 
@@ -2335,7 +2335,7 @@ static void CBTSetVrefLP4(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefLevel, U8 ope
 
 		u4DbgValue = (((u1VrefRange & 0x1) << 6) | (u1VrefLevel & 0x3f));
 		u1MR12Value[p->channel][p->rank][operating_fsp] = u4DbgValue;
-		mcSHOW_DBG_MSG3(("u4DbgValue = 0x%x\n", u4DbgValue));
+		msg3("u4DbgValue = 0x%x\n", u4DbgValue);
 
 		DramcModeRegWriteByRank(p, p->rank, 12, u4DbgValue);
 	}
@@ -3044,7 +3044,7 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
 	}
 
 #if MRW_CHECK_ONLY
-	mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+	mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
 
 #if __LP5_COMBO__
@@ -3078,13 +3078,13 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
 #endif
 
 	vPrintCalibrationBasicInfo(p);
-	mcSHOW_DBG_MSG(("pi_start=%d, pi_end=%d, pi_step=%d, new_cbt_mode=%d, autok=%d\n",
-			pi_start, pi_end, pi_step, p->new_cbt_mode, autok));
+	msg("pi_start=%d, pi_end=%d, pi_step=%d, new_cbt_mode=%d, autok=%d\n",
+			pi_start, pi_end, pi_step, p->new_cbt_mode, autok);
 
 #if __LP5_COMBO__
 	if (is_lp5_family(p))
 	{
-		mcSHOW_DBG_MSG(("lp5_training_mode=%d, lp5_cbt_phase=%d\n", p->lp5_training_mode, p->lp5_cbt_phase));
+		msg("lp5_training_mode=%d, lp5_cbt_phase=%d\n", p->lp5_training_mode, p->lp5_cbt_phase);
 	}
 #endif
 
@@ -3172,7 +3172,7 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
 	}
 #endif
 
-	mcSHOW_DBG_MSG(("\n[CmdBusTrainingLP45] Vref(ca) range %d: %d\n", u1FinalRange, u1FinalVref));
+	msg("\n[CmdBusTrainingLP45] Vref(ca) range %d: %d\n", u1FinalRange, u1FinalVref);
 
 #ifdef FOR_HQA_TEST_USED
 	gFinalCBTVrefCA[p->channel][p->rank] = u1FinalVref;
@@ -3196,7 +3196,7 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
 	gEyeScan_CaliDelay[0] = CATrain_CmdDelay[p->channel][p->rank] -pi_start;
 #endif
 
-	//mcSHOW_DBG_MSG(("\nAverage CA Dly: %d\n", iFinalCACLK));
+	//msg("\nAverage CA Dly: %d\n", iFinalCACLK);
 
 	/* -------------  CS and CLK ---------- */
 	/* delay ca 1UI before K CS */
@@ -3244,7 +3244,7 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
 	gFinalCBTVrefDQ[p->channel][p->rank] = u1FinalVref;
 #endif
 
-	mcSHOW_DBG_MSG3(("\n[CmdBusTrainingLP45] Done\n"));
+	msg3("\n[CmdBusTrainingLP45] Done\n");
 
 	//tx_rank_sel is selected by HW //Lewis@20180509: tx_rank_sel is selected by SW in CBT if TMRRI design has changed.
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), 0, TX_SET0_TXRANK);
@@ -3315,7 +3315,7 @@ static DRAM_STATUS_T ExecuteMoveDramCDelay(DRAMC_CTX_T *p,
 
 	u4TmpUI = u4IO32ReadFldAlign(DRAMC_REG_ADDR(ui_reg.u4Addr), ui_reg.u4Fld) & (~(1 << ucDataRateDivShift));
 	u4TmpMCK = u4IO32ReadFldAlign(DRAMC_REG_ADDR(mck_reg.u4Addr), mck_reg.u4Fld);
-	//mcSHOW_DBG_MSG(("Base:  u4TmpMCK:%d,	u4TmpUI: %d,\n", u4TmpMCK, u4TmpUI));
+	//msg("Base:  u4TmpMCK:%d,	u4TmpUI: %d,\n", u4TmpMCK, u4TmpUI);
 
 	s4HighLevelDelay = (u4TmpMCK << ucDataRateDivShift) + u4TmpUI;
 	s4DelaySum = (s4HighLevelDelay + iShiftUI);
@@ -3335,7 +3335,7 @@ static DRAM_STATUS_T ExecuteMoveDramCDelay(DRAMC_CTX_T *p,
 
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(ui_reg.u4Addr), u4TmpUI, ui_reg.u4Fld);
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(mck_reg.u4Addr), u4TmpMCK, mck_reg.u4Fld);
-	//mcSHOW_DBG_MSG(("[%d]  Final ==> u4TmpMCK:%d,  u4TmpUI: %d,\n", iShiftUI, u4TmpMCK, u4TmpUI));
+	//msg("[%d]  Final ==> u4TmpMCK:%d,  u4TmpUI: %d,\n", iShiftUI, u4TmpMCK, u4TmpUI);
 
 	return MoveResult;
 }
@@ -3511,7 +3511,7 @@ static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerR
 
 	if (u4TimeCnt == 0)//time out
 	{
-		mcSHOW_DBG_MSG(("[DramcTriggerAndWait] Wait 0x%x respond fail (time out)\n", RepondsReg.u4Addr));
+		msg("[DramcTriggerAndWait] Wait 0x%x respond fail (time out)\n", RepondsReg.u4Addr);
 		return DRAM_FAIL;
 	}
 
@@ -3524,7 +3524,7 @@ static DRAM_STATUS_T DramcTriggerAndWait(DRAMC_CTX_T *p, REG_TRANSFER_T TriggerR
 #define ASSERT(x) \
 		if (!(x)) \
 			while (1)\
-				mcSHOW_ERR_MSG(("ASSERT FAIL at %s[%d]!\n", __FUNCTION__, __LINE__));
+				err("ASSERT FAIL at %s[%d]!\n", __FUNCTION__, __LINE__);
 #endif
 
 
@@ -3567,7 +3567,7 @@ static void WriteLevelingScanRange_PI(DRAMC_CTX_T *p, S32 *ps4DlyBegin, S32 *ps4
 		u1PIStep = 1;	 // One step is 1/4 delay cell
 		PI_bound = 1024; // No bounadary as delay cell based
 	}
-	mcSHOW_DBG_MSG2(("Begin: %d, End: %d, Step: %d, Bound: %d\n", s4DlyBegin, s4DlyEnd, u1PIStep, PI_bound));
+	msg2("Begin: %d, End: %d, Step: %d, Bound: %d\n", s4DlyBegin, s4DlyEnd, u1PIStep, PI_bound);
 
 	*ps4DlyBegin = s4DlyBegin;
 	*ps4DlyEnd = s4DlyEnd;
@@ -3588,7 +3588,7 @@ DRAM_STATUS_T WriteLevelingPosCal(DRAMC_CTX_T *p, WLEV_DELAY_BASED_T stDelayBase
 		(wrlevel_dqs_final_delay[RANK_0][1] - wrlevel_dqs_final_delay[RANK_1][1])>=9 ||
 		(wrlevel_dqs_final_delay[RANK_0][1] - wrlevel_dqs_final_delay[RANK_1][1])<=-9 )
 	{
-		mcSHOW_ERR_MSG(("[WARNING] Larger WL R2R !!\n"));
+		err("[WARNING] Larger WL R2R !!\n");
 		#if CHECK_HQA_CRITERIA
 		while(1);
 		#endif
@@ -3622,7 +3622,7 @@ DRAM_STATUS_T WriteLevelingPosCal(DRAMC_CTX_T *p, WLEV_DELAY_BASED_T stDelayBase
 
 	vSetRank(p, backup_rank);
 
-	mcSHOW_DBG_MSG(("[WriteLevelingPosCal] DQS PI B0/B1 = %d/%d\n", wrlevel_dqs_delay[0], wrlevel_dqs_delay[1]));
+	msg("[WriteLevelingPosCal] DQS PI B0/B1 = %d/%d\n", wrlevel_dqs_delay[0], wrlevel_dqs_delay[1]);
 }
 #endif
 
@@ -3648,7 +3648,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
 	// error handling
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context NULL\n"));
+		err("context NULL\n");
 		return DRAM_FAIL;
 	}
 
@@ -3688,7 +3688,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
 	vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, DRAM_FAIL);
 
 #if MRW_CHECK_ONLY
-	mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+	mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
 
 	if (p->isWLevInitShift[p->channel] == FALSE)
@@ -3760,7 +3760,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
 		#endif
 	}
 	vSetCalibrationResult(p, DRAM_CALIBRATION_WRITE_LEVEL, KResult);
-	mcSHOW_DBG_MSG2(("pass bytecount = 0x%x (0xff: all bytes pass) \n\n", ucDoneFlg));
+	msg2("pass bytecount = 0x%x (0xff: all bytes pass) \n\n", ucDoneFlg);
 
 #if defined(FOR_HQA_TEST_USED) && defined(FOR_HQA_REPORT_USED)
 	if (gHQALog_flag == 1)
@@ -3797,8 +3797,8 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
 	// Calculate DQS "PI" delay, nothing to do with delay cell
 	for (byte_i = 0; byte_i < (p->data_width / DQS_BIT_NUMBER); byte_i++)
 	{
-		mcSHOW_DBG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i]));
-		mcDUMP_REG_MSG(("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i]));
+		msg("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i]);
+		reg_msg("Write leveling (Byte %d): %d", byte_i, wrlevel_dqs_final_delay[p->rank][byte_i]);
 		if (wrlevel_dqs_final_delay[p->rank][byte_i] >= PI_bound)
 		{
 			ShiftDQSWCK_UI(p, (wrlevel_dqs_final_delay[p->rank][byte_i] / PI_bound) * (PI_bound / DQPI_PER_UI), byte_i);
@@ -3807,8 +3807,8 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
 		}
 
 		wrlevel_dqs_delay[byte_i] = wrlevel_dqs_final_delay[p->rank][byte_i];
-		mcSHOW_DBG_MSG((" => %d\n", wrlevel_dqs_delay[byte_i]));
-		mcDUMP_REG_MSG((" => %d\n", wrlevel_dqs_delay[byte_i]));
+		msg(" => %d\n", wrlevel_dqs_delay[byte_i]);
+		reg_msg(" => %d\n", wrlevel_dqs_delay[byte_i]);
 	}
 
 	for (rank_i = p->rank; rank_i < RANK_MAX; rank_i++)
@@ -3833,7 +3833,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
 
 	vSetRank(p, backup_rank);
 
-	mcSHOW_DBG_MSG3(("[DramcWriteLeveling] Done\n\n"));
+	msg3("[DramcWriteLeveling] Done\n\n");
 
 	return KResult;
 }
@@ -3856,7 +3856,7 @@ DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p)
 	// error handling
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context NULL\n"));
+		err("context NULL\n");
 		return DRAM_FAIL;
 	}
 
@@ -3872,7 +3872,7 @@ DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p)
 	{
 		// MRW MR30 OP[7:4] = i(Set DCAU) and OP[3:0] = i(Set DCAL)
 		U8 u8RGSettingVal = FetchRGSettingVal(i);
-		mcSHOW_ERR_MSG(("Set value %d into MR30\n", u8RGSettingVal));
+		err("Set value %d into MR30\n", u8RGSettingVal);
 		MRWriteFldMulti(p, 30, P_Fld(u8RGSettingVal, MR30_DCAU) |
 							   P_Fld(u8RGSettingVal, MR30_DCAL),
 							   TO_MR);
@@ -3901,7 +3901,7 @@ DRAM_STATUS_T DramcDutyCycleMonitor(DRAMC_CTX_T *p)
 		// Delay tMRD
 		mcDELAY_US(2);
 
-		mcSHOW_ERR_MSG(("Wait tMRD and MRR MR26\n"));
+		err("Wait tMRD and MRR MR26\n");
 
 		///TODO:  Read back result MR25[5:2]
 		// Store result into u8ResultDutyCycMonitor[]
@@ -4017,8 +4017,8 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
 	u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
 
-	mcSHOW_DBG_MSG3(("[ZQCalibration]\n"));
-	//mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
+	msg3("[ZQCalibration]\n");
+	//mcFPRINTF(fp_A60501, "[ZQCalibration]\n");
 
 	// Disable HW MIOCK control to make CLK always on
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF);
@@ -4040,8 +4040,8 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 		u4TimeCnt --;
 		mcDELAY_US(1);	// Wait tZQCAL(min) 1us or wait next polling
 
-		mcSHOW_DBG_MSG3(("%d- ", u4TimeCnt));
-		//mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
+		msg3("%d- ", u4TimeCnt);
+		//mcFPRINTF(fp_A60501, "%d- ", u4TimeCnt);
 	}while((u4Response==0) &&(u4TimeCnt>0));
 
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN_SWTRIG);
@@ -4049,8 +4049,8 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	if(u4TimeCnt==0)//time out
 	{
 		vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
-		mcSHOW_DBG_MSG(("ZQCAL Start fail (time out)\n"));
-		//mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
+		msg("ZQCAL Start fail (time out)\n");
+		//mcFPRINTF(fp_A60501, "ZQCAL Start fail (time out)\n");
 		return DRAM_FAIL;
 	}
 
@@ -4066,8 +4066,8 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 		u4TimeCnt --;
 		mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling
 
-		mcSHOW_DBG_MSG3(("%d=", u4TimeCnt));
-		//mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt));
+		msg3("%d=", u4TimeCnt);
+		//mcFPRINTF(fp_A60501, "%d= ", u4TimeCnt);
 	}while((u4Response==0) &&(u4TimeCnt>0));
 
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN_SWTRIG);
@@ -4075,8 +4075,8 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	if(u4TimeCnt==0)//time out
 	{
 		vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
-		mcSHOW_DBG_MSG(("ZQCAL Latch fail (time out)\n"));
-		//mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n"));
+		msg("ZQCAL Latch fail (time out)\n");
+		//mcFPRINTF(fp_A60501, "ZQCAL Latch fail (time out)\n");
 		return DRAM_FAIL;
 	}
 
@@ -4090,8 +4090,8 @@ static DRAM_STATUS_T ZQ_SWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL);
 
 	vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK);
-	mcSHOW_DBG_MSG3(("\n[DramcZQCalibration] Done\n\n"));
-	//mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
+	msg3("\n[DramcZQCalibration] Done\n\n");
+	//mcFPRINTF(fp_A60501, "\n[DramcZQCalibration] Done\n\n");
 
 	return DRAM_OK;
 }
@@ -4111,8 +4111,8 @@ DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
 	u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
 
-	mcSHOW_DBG_MSG3(("[ZQCalibration]\n"));
-	//mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
+	msg3("[ZQCalibration]\n");
+	//mcFPRINTF(fp_A60501, "[ZQCalibration]\n");
 
 	// Disable HW MIOCK control to make CLK always on
 	//vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF);
@@ -4140,8 +4140,8 @@ DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 		u4TimeCnt --;
 		mcDELAY_US(1);	// Wait tZQCAL(min) 1us or wait next polling
 
-		mcSHOW_DBG_MSG3(("%d- ", u4TimeCnt));
-		//mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
+		msg3("%d- ", u4TimeCnt);
+		//mcFPRINTF(fp_A60501, "%d- ", u4TimeCnt);
 	}while((u4Response==0) &&(u4TimeCnt>0));
 
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN);
@@ -4149,8 +4149,8 @@ DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	if(u4TimeCnt==0)//time out
 	{
 		vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
-		mcSHOW_DBG_MSG(("ZQCAL Start fail (time out)\n"));
-		//mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
+		msg("ZQCAL Start fail (time out)\n");
+		//mcFPRINTF(fp_A60501, "ZQCAL Start fail (time out)\n");
 		return DRAM_FAIL;
 	}
 
@@ -4168,8 +4168,8 @@ DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 		u4TimeCnt --;
 		mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling
 
-		mcSHOW_DBG_MSG3(("%d=", u4TimeCnt));
-		//mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt));
+		msg3("%d=", u4TimeCnt);
+		//mcFPRINTF(fp_A60501, "%d= ", u4TimeCnt);
 	}while((u4Response==0) &&(u4TimeCnt>0));
 
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_RTSWCMDEN);
@@ -4177,8 +4177,8 @@ DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	if(u4TimeCnt==0)//time out
 	{
 		vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
-		mcSHOW_DBG_MSG(("ZQCAL Latch fail (time out)\n"));
-		//mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n"));
+		msg("ZQCAL Latch fail (time out)\n");
+		//mcFPRINTF(fp_A60501, "ZQCAL Latch fail (time out)\n");
 		return DRAM_FAIL;
 	}
 
@@ -4194,8 +4194,8 @@ DRAM_STATUS_T ZQ_RTSWCMD_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL);
 
 	vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK);
-	mcSHOW_DBG_MSG3(("\n[DramcZQCalibration] Done\n\n"));
-	//mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
+	msg3("\n[DramcZQCalibration] Done\n\n");
+	//mcFPRINTF(fp_A60501, "\n[DramcZQCalibration] Done\n\n");
 
 	return DRAM_OK;
 }
@@ -4214,8 +4214,8 @@ DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	u4SPDCTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
 	u4CKECTRL = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL));
 
-	mcSHOW_DBG_MSG3(("[ZQCalibration]\n"));
-	//mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
+	msg3("[ZQCalibration]\n");
+	//mcFPRINTF(fp_A60501, "[ZQCalibration]\n");
 
 	// Disable HW MIOCK control to make CLK always on
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF);
@@ -4242,8 +4242,8 @@ DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 		u4TimeCnt --;
 		mcDELAY_US(1);	// Wait tZQCAL(min) 1us or wait next polling
 
-		mcSHOW_DBG_MSG3(("%d- ", u4TimeCnt));
-		//mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
+		msg3("%d- ", u4TimeCnt);
+		//mcFPRINTF(fp_A60501, "%d- ", u4TimeCnt);
 	}while((u4Response==0) &&(u4TimeCnt>0));
 
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQCEN);
@@ -4251,8 +4251,8 @@ DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	if(u4TimeCnt==0)//time out
 	{
 		vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
-		mcSHOW_DBG_MSG(("ZQCAL Start fail (time out)\n"));
-		//mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
+		msg("ZQCAL Start fail (time out)\n");
+		//mcFPRINTF(fp_A60501, "ZQCAL Start fail (time out)\n");
 		return DRAM_FAIL;
 	}
 
@@ -4271,8 +4271,8 @@ DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 		u4TimeCnt --;
 		mcDELAY_US(1);// Wait tZQLAT 30ns or wait next polling
 
-		mcSHOW_DBG_MSG3(("%d=", u4TimeCnt));
-		//mcFPRINTF((fp_A60501, "%d= ", u4TimeCnt));
+		msg3("%d=", u4TimeCnt);
+		//mcFPRINTF(fp_A60501, "%d= ", u4TimeCnt);
 	}while((u4Response==0) &&(u4TimeCnt>0));
 
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_ZQLATEN);
@@ -4280,8 +4280,8 @@ DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	if(u4TimeCnt==0)//time out
 	{
 		vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_FAIL);
-		mcSHOW_DBG_MSG(("ZQCAL Latch fail (time out)\n"));
-		//mcFPRINTF((fp_A60501, "ZQCAL Latch fail (time out)\n"));
+		msg("ZQCAL Latch fail (time out)\n");
+		//mcFPRINTF(fp_A60501, "ZQCAL Latch fail (time out)\n");
 		return DRAM_FAIL;
 	}
 
@@ -4296,8 +4296,8 @@ DRAM_STATUS_T ZQ_SCSM_MODE_Cal(DRAMC_CTX_T *p, U8 rank)
 	vIO32Write4B(DRAMC_REG_ADDR(DRAMC_REG_CKECTRL), u4CKECTRL);
 
 	vSetCalibrationResult(p, DRAM_CALIBRATION_ZQ, DRAM_OK);
-	mcSHOW_DBG_MSG3(("\n[DramcZQCalibration] Done\n\n"));
-	//mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
+	msg3("\n[DramcZQCalibration] Done\n\n");
+	//mcFPRINTF(fp_A60501, "\n[DramcZQCalibration] Done\n\n");
 
 	return DRAM_OK;
 }
@@ -4423,8 +4423,8 @@ static U8 u1GetLp5ReadLatency(DRAMC_CTX_T *p)
 	else
 		read_latency *= 2;
 
-	mcSHOW_DBG_MSG(("ckr = %d, dvfsc = %d, rl = %d, read_latency = %d\n",
-		ckr, dvfsc, rl, read_latency));
+	msg("ckr = %d, dvfsc = %d, rl = %d, read_latency = %d\n",
+		ckr, dvfsc, rl, read_latency);
 
 	return read_latency;
 }
@@ -4511,24 +4511,24 @@ static U8 u1GetGatingStartPos(DRAMC_CTX_T *p, U8 u1AutoK)
 	else
 	{
 		u1StartUI =0;
-		mcSHOW_ERR_MSG(("GatingStartPos err! Need to fine-tune default DQSINCTL value.\n(RX_Path_delay_UI %d) < DQSINCTL_UI %d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI));
+		err("GatingStartPos err! Need to fine-tune default DQSINCTL value.\n(RX_Path_delay_UI %d) < DQSINCTL_UI %d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI);
 		#if __ETT__
 		while(1);
 		#endif
 	}
 
-	mcSHOW_DBG_MSG(("[GatingStartPos] MR0_LatencyMode %d, u1RealRL %d , u4TDQSCK_UI_min %d, 1:4ExtraMCK %d\n", u1MR0_LatencyMode, u1RealRL, u4TDQSCK_UI_min, u1ExtraMCKfor1_4mode));
-	mcDUMP_REG_MSG(("[GatingStartPos] MR0_LatencyMode %d, u1RealRL %d , u4TDQSCK_UI_min %d, 1:4ExtraMCK %d\n", u1MR0_LatencyMode, u1RealRL, u4TDQSCK_UI_min, u1ExtraMCKfor1_4mode));
+	msg("[GatingStartPos] MR0_LatencyMode %d, u1RealRL %d , u4TDQSCK_UI_min %d, 1:4ExtraMCK %d\n", u1MR0_LatencyMode, u1RealRL, u4TDQSCK_UI_min, u1ExtraMCKfor1_4mode);
+	reg_msg("[GatingStartPos] MR0_LatencyMode %d, u1RealRL %d , u4TDQSCK_UI_min %d, 1:4ExtraMCK %d\n", u1MR0_LatencyMode, u1RealRL, u4TDQSCK_UI_min, u1ExtraMCKfor1_4mode);
 
 	if(u1AutoK)
 	{
-		mcSHOW_DBG_MSG(("RX_Path_delay_UI(%d) - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI));
-		mcDUMP_REG_MSG(("RX_Path_delay_UI(%d) - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI));
+		msg("RX_Path_delay_UI(%d) - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI);
+		reg_msg("RX_Path_delay_UI(%d) - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI);
 	}
 	else
 	{
-		mcSHOW_DBG_MSG(("RX_Path_delay_UI(%d) -3 - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI));
-		mcDUMP_REG_MSG(("RX_Path_delay_UI(%d) -3 - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI));
+		msg("RX_Path_delay_UI(%d) -3 - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI);
+		reg_msg("RX_Path_delay_UI(%d) -3 - DQSINCTL_UI(%d) = u1StartUI(%d)\n", u1RX_Path_delay_UI, u1DQSINCTL_UI, u1StartUI);
 	}
 
 	return u1StartUI;
@@ -4550,7 +4550,7 @@ static u8 rxdqs_gating_bypass(DRAMC_CTX_T *p)
 {
 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_GatingCal
 		if (p->femmc_Ready == 1) {
-			mcSHOW_DBG_MSG(("[FAST_K] Bypass Gating Calibration\n"));
+			msg("[FAST_K] Bypass Gating Calibration\n");
 			return 1;
 		}
 #endif
@@ -4590,14 +4590,14 @@ static void rxdqs_gating_fastk_save_restore(DRAMC_CTX_T *p,
 
 				vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAST_K);
 
-				mcSHOW_DBG_MSG(("[FAST_K] CH%d RK%d best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n",
+				msg("[FAST_K] CH%d RK%d best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n",
 					ch, rk, dqs_i, best_win->best_dqsien_dly_mck[dqs_i],
 					best_win->best_dqsien_dly_ui[dqs_i],
-					best_win->best_dqsien_dly_pi[dqs_i]));
-				mcSHOW_DBG_MSG(("[FAST_K] CH%d RK%d best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n",
+					best_win->best_dqsien_dly_pi[dqs_i]);
+				msg("[FAST_K] CH%d RK%d best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n",
 					ch, rk, dqs_i, best_win->best_dqsien_dly_mck_p1[dqs_i],
 					best_win->best_dqsien_dly_ui_p1[dqs_i],
-					best_win->best_dqsien_dly_pi_p1[dqs_i]));
+					best_win->best_dqsien_dly_pi_p1[dqs_i]);
 
 			}
 		}
@@ -4642,18 +4642,18 @@ static void rxdqs_gating_misc_process(DRAMC_CTX_T *p,
 #endif
 
 		/*TINFO="best DQS%d delay(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win.best_dqsien_dly_mck[dqs_i], rxdqs_best_win.best_dqsien_dly_ui[dqs_i], rxdqs_best_win.best_dqsien_dly_pi[dqs_i])); */
-		mcSHOW_DBG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+		msg("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
 			rxdqs_best_win->best_dqsien_dly_mck[dqs_i],
 			rxdqs_best_win->best_dqsien_dly_ui[dqs_i],
-			rxdqs_best_win->best_dqsien_dly_pi[dqs_i]));
-		mcDUMP_REG_MSG(("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+			rxdqs_best_win->best_dqsien_dly_pi[dqs_i]);
+		reg_msg("best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
 			rxdqs_best_win->best_dqsien_dly_mck[dqs_i],
 			rxdqs_best_win->best_dqsien_dly_ui[dqs_i],
-			rxdqs_best_win->best_dqsien_dly_pi[dqs_i]));
-		/* cc mark mcFPRINTF((fp_A60501,"best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+			rxdqs_best_win->best_dqsien_dly_pi[dqs_i]);
+		/* cc mark mcFPRINTF(fp_A60501,"best DQS%d dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
 			rxdqs_best_win.best_dqsien_dly_mck[dqs_i],
 			rxdqs_best_win.best_dqsien_dly_ui[dqs_i],
-			rxdqs_best_win.best_dqsien_dly_pi[dqs_i]));
+			rxdqs_best_win.best_dqsien_dly_pi[dqs_i]);
 		*/
 
 #if GATING_ADJUST_TXDLY_FOR_TRACKING
@@ -4675,23 +4675,23 @@ static void rxdqs_gating_misc_process(DRAMC_CTX_T *p,
 #endif
 	}
 
-	mcSHOW_DBG_MSG(("\n"));
-	//cc mark mcFPRINTF((fp_A60501,"\n"));
+	msg("\n");
+	//cc mark mcFPRINTF(fp_A60501,"\n");
 
 	for (dqs_i=0; dqs_i<(p->data_width/DQS_BIT_NUMBER); dqs_i++) {
 		/*TINFO="best DQS%d P1 delay(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i, rxdqs_best_win.best_dqsien_dly_mck_p1[dqs_i], rxdqs_best_win.best_dqsien_dly_ui_p1[dqs_i], rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i]*/
-		mcSHOW_DBG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+		msg("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
 			rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i],
 			rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i],
-			rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i]));
-		mcDUMP_REG_MSG(("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
+			rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i]);
+		reg_msg("best DQS%d P1 dly(MCK, UI, PI) = (%d, %d, %d)\n", dqs_i,
 			rxdqs_best_win->best_dqsien_dly_mck_p1[dqs_i],
 			rxdqs_best_win->best_dqsien_dly_ui_p1[dqs_i],
-			rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i]));
-		/* cc mark mcFPRINTF((fp_A60501,"best DQS%d P1 dly(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i,
+			rxdqs_best_win->best_dqsien_dly_pi_p1[dqs_i]);
+		/* cc mark mcFPRINTF(fp_A60501,"best DQS%d P1 dly(2T, 0.5T, PI) = (%d, %d, %d)\n", dqs_i,
 			rxdqs_best_win.best_dqsien_dly_mck_p1[dqs_i],
 			rxdqs_best_win.best_dqsien_dly_ui_p1[dqs_i],
-			rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i]));
+			rxdqs_best_win.best_dqsien_dly_pi_p1[dqs_i]);
 		*/
 
 #if GATING_ADJUST_TXDLY_FOR_TRACKING
@@ -4868,24 +4868,24 @@ static void rxdqs_gating_auto_cal_cfg(DRAMC_CTX_T *p,
 		P_Fld(0x0, MISC_SHU_STBCAL_STBCALEN) |
 		P_Fld(0x0, MISC_SHU_STBCAL_STB_SELPHCALEN));
 
-	mcSHOW_DBG_MSG(("[Gating] AUTO K with param:\n"));
-	mcSHOW_DBG_MSG(("\tinit_mck: %d, init_ui: %d, end_mck: %d, end_ui: %d\n",
+	msg("[Gating] AUTO K with param:\n");
+	msg("\tinit_mck: %d, init_ui: %d, end_mck: %d, end_ui: %d\n",
 		auto_param->init_mck, auto_param->init_ui,
-		auto_param->end_mck, auto_param->end_ui));
-	mcSHOW_DBG_MSG(("\tpi_offset: %d, early_break: %s\n", auto_param->pi_offset,
-		(auto_param->early_break)? "ENABLE" : "DISABLE"));
+		auto_param->end_mck, auto_param->end_ui);
+	msg("\tpi_offset: %d, early_break: %s\n", auto_param->pi_offset,
+		(auto_param->early_break)? "ENABLE" : "DISABLE");
 }
 
 static void rxdqs_gating_auto_cal_trigger(DRAMC_CTX_T *p)
 {
-	mcSHOW_DBG_MSG(("[Gating] AUTO K start...\n"));
+	msg("[Gating] AUTO K start...\n");
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
 		0x1, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO);
 }
 
 static void rxdqs_gating_auto_cal_stop(DRAMC_CTX_T *p)
 {
-	mcSHOW_DBG_MSG(("[Gating] AUTO K stop...\n"));
+	msg("[Gating] AUTO K stop...\n");
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DQSIEN_AUTOK_CFG0),
 		0x0, MISC_DQSIEN_AUTOK_CFG0_DQSIEN_AUTOK_GO);
 
@@ -4926,14 +4926,14 @@ static void rxdqs_gating_set_final_result(DRAMC_CTX_T *p, U8 mck2ui,
 			reg_ui_rodt[dqs_i] = 0;
 			reg_mck_rodt_p1[dqs_i] = 4;
 			reg_ui_rodt_p1[dqs_i] = 4;
-			mcSHOW_DBG_MSG(("[Warning] RODT cannot be -11UI for B%d\n",
-				dqs_i));
+			msg("[Warning] RODT cannot be -11UI for B%d\n",
+				dqs_i);
 		}
 
-		mcSHOW_DBG_MSG(("DQS%d Final RODTEN: (%2d, %2d)\n",
-			dqs_i, reg_mck_rodt[dqs_i], reg_ui_rodt[dqs_i]));
-		mcSHOW_DBG_MSG(("DQS%d Final RODTEN_P1: (%2d, %2d)\n",
-			dqs_i, reg_mck_rodt_p1[dqs_i], reg_ui_rodt_p1[dqs_i]));
+		msg("DQS%d Final RODTEN: (%2d, %2d)\n",
+			dqs_i, reg_mck_rodt[dqs_i], reg_ui_rodt[dqs_i]);
+		msg("DQS%d Final RODTEN_P1: (%2d, %2d)\n",
+			dqs_i, reg_mck_rodt_p1[dqs_i], reg_ui_rodt_p1[dqs_i]);
 	}
 #endif
 
@@ -5029,8 +5029,8 @@ static void rxdqs_gating_auto_xlate(DRAMC_CTX_T *p,
 		mck_p1 = (value + freq_div) / mck2ui;
 		ui_p1 = (value + freq_div) % mck2ui;
 
-		mcSHOW_DBG_MSG(("[Gating][RG] DQS%d Final result: (%d, %d, %d)\n", dqs_i, mck, ui, pi));
-		mcSHOW_DBG_MSG(("[Gating][RG] DQS%d Final result P1: (%d, %d)\n", dqs_i, mck_p1, ui_p1));
+		msg("[Gating][RG] DQS%d Final result: (%d, %d, %d)\n", dqs_i, mck, ui, pi);
+		msg("[Gating][RG] DQS%d Final result P1: (%d, %d)\n", dqs_i, mck_p1, ui_p1);
 
 		best_win->best_dqsien_dly_mck[dqs_i] = mck;
 		best_win->best_dqsien_dly_ui[dqs_i] = ui;
@@ -5131,8 +5131,8 @@ static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p,
 						dbg_reg_idx++, dbg_reg_addr += 4) {
 						dbg_reg_val = u4IO32Read4B(dbg_reg_addr);
 
-						mcSHOW_ERR_MSG(("B%d Gating AUTOK DBG Status-%d: [0x%08x]\n",
-							dqs_i, dbg_reg_idx, dbg_reg_val));
+						err("B%d Gating AUTOK DBG Status-%d: [0x%08x]\n",
+							dqs_i, dbg_reg_idx, dbg_reg_val);
 					}
 				}
 				done_bytes++;
@@ -5144,19 +5144,19 @@ static DRAM_STATUS_T rxdqs_gating_auto_cal_status(DRAMC_CTX_T *p,
 
 	/* Log it */
 	for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++) {
-		mcSHOW_DBG_MSG(("[Gating][%s] AUTOK of CH-%d, Rk-%d, Byte-%d:\n",
-			error[dqs_i]? "Fail" : "Pass", p->channel, p->rank, dqs_i));
+		msg("[Gating][%s] AUTOK of CH-%d, Rk-%d, Byte-%d:\n",
+			error[dqs_i]? "Fail" : "Pass", p->channel, p->rank, dqs_i);
 
 		if (done[dqs_i]) {
 			if (error[dqs_i] == 0) {
-				mcSHOW_DBG_MSG(("\tcenter(%2d, %2d, %2d)\n",
-							mck_center[dqs_i], ui_center[dqs_i], pi_center[dqs_i]));
-				mcSHOW_DBG_MSG(("\tleft(%2d, %2d, %2d)\n",
-							mck_left[dqs_i], ui_left[dqs_i], pi_left[dqs_i]));
+				msg("\tcenter(%2d, %2d, %2d)\n",
+							mck_center[dqs_i], ui_center[dqs_i], pi_center[dqs_i]);
+				msg("\tleft(%2d, %2d, %2d)\n",
+							mck_left[dqs_i], ui_left[dqs_i], pi_left[dqs_i]);
 
 				if (auto_param->early_break == DISABLE) {
-					mcSHOW_DBG_MSG(("\tright(%2d, %2d, %2d)\n",
-								mck_right[dqs_i], ui_right[dqs_i], pi_right[dqs_i]));
+					msg("\tright(%2d, %2d, %2d)\n",
+								mck_right[dqs_i], ui_right[dqs_i], pi_right[dqs_i]);
 				}
 			}
 			if (error[dqs_i]) {
@@ -5413,7 +5413,7 @@ static void rxdqs_gating_set_dqsien_dly(DRAMC_CTX_T *p, U8 dly_ui,
 		reg_ui_rodt = 0;
 		reg_mck_rodt_p1 = 4;
 		reg_ui_rodt_p1 = 4;
-		mcSHOW_DBG_MSG(("[Warning] RODT cannot be -11UI\n"));
+		msg("[Warning] RODT cannot be -11UI\n");
 	}
 #endif
 
@@ -5607,14 +5607,14 @@ static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p,
 	/* read (lead, lag) */
 	rxdqs_gating_get_leadlag(p, rxdqs_trans, rxdqs_cal);
 
-	mcSHOW_DBG_MSG(("%2d %2d %2d | ",
+	msg("%2d %2d %2d | ",
 		rxdqs_cal->dqsien_dly_mck, rxdqs_cal->dqsien_dly_ui,
-		rxdqs_cal->dqsien_dly_pi));
-	mcSHOW_DBG_MSG(("B1->B0 | %x %x | %x %x | (%d %d) (%d %d)\n",
+		rxdqs_cal->dqsien_dly_pi);
+	msg("B1->B0 | %x %x | %x %x | (%d %d) (%d %d)\n",
 		debug_cnt[1], debug_cnt[0],
 		gating_error[1], gating_error[0],
 		rxdqs_trans->dqs_lead[1], rxdqs_trans->dqs_lag[1],
-		rxdqs_trans->dqs_lead[0], rxdqs_trans->dqs_lag[0]));
+		rxdqs_trans->dqs_lead[0], rxdqs_trans->dqs_lag[0]);
 
 #if (__LP5_COMBO__)
 	if((is_lp5_family(p)) && (vGet_Div_Mode(p) == DIV16_MODE))
@@ -5657,18 +5657,18 @@ static U8 rxdqs_gating_sw_cal(DRAMC_CTX_T *p,
 				best_win->best_dqsien_dly_ui_p1[dqs_i] =
 					best_win->best_dqsien_dly_mck[dqs_i] * mck2ui +
 					best_win->best_dqsien_dly_ui[dqs_i] + freq_div; /* Total UI for Phase1 */
-				mcSHOW_DBG_MSG(("Total UI for P1: %d, mck2ui %d\n",
-					best_win->best_dqsien_dly_mck_p1[dqs_i], mck2ui));
+				msg("Total UI for P1: %d, mck2ui %d\n",
+					best_win->best_dqsien_dly_mck_p1[dqs_i], mck2ui);
 				best_win->best_dqsien_dly_mck_p1[dqs_i] =
 					best_win->best_dqsien_dly_ui_p1[dqs_i] / mck2ui;
 				best_win->best_dqsien_dly_ui_p1[dqs_i] =
 					best_win->best_dqsien_dly_ui_p1[dqs_i] % mck2ui;
 
-				mcSHOW_DBG_MSG(("best dqsien dly found for B%d: "
+				msg("best dqsien dly found for B%d: "
 					"(%2d, %2d, %2d)\n", dqs_i,
 					best_win->best_dqsien_dly_mck[dqs_i],
 					best_win->best_dqsien_dly_ui[dqs_i],
-					best_win->best_dqsien_dly_pi[dqs_i]));
+					best_win->best_dqsien_dly_pi[dqs_i]);
 				passed_bytes |= 1 << dqs_i;
 
 				if (((p->data_width == DATA_WIDTH_16BIT) &&
@@ -5706,7 +5706,7 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p,
 	U8 u1GatingErrorFlag=0;
 
 	if (p == NULL) {
-		mcSHOW_ERR_MSG(("[Error] Context NULL\n"));
+		err("[Error] Context NULL\n");
 		return DRAM_FAIL;
 	}
 
@@ -5817,7 +5817,7 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p,
 			{
 				u1GatingErrorFlag=1;
 				/*TINFO="error, no pass taps in DQS_%d !!!\n", dqs_i*/
-				mcSHOW_ERR_MSG(("error, no pass taps in DQS_%d!\n", dqs_i));
+				err("error, no pass taps in DQS_%d!\n", dqs_i);
 			}
 		}
 	if (u1GatingErrorFlag==0)
@@ -5846,7 +5846,7 @@ static DRAM_STATUS_T dramc_rx_dqs_gating_sw_cal(DRAMC_CTX_T *p,
 	rxdqs_gating_fastk_save_restore(p, &rxdqs_best_win, &rxdqs_cal);
 	rxdqs_gating_misc_process(p, &rxdqs_best_win);
 
-	mcSHOW_DBG_MSG(("[Gating] SW calibration Done\n"));
+	msg("[Gating] SW calibration Done\n");
 
 	/* Set MCK & UI */
 	rxdqs_gating_set_final_result(p, ui_per_mck, &rxdqs_best_win);
@@ -5892,10 +5892,10 @@ DRAM_STATUS_T dramc_rx_dqs_gating_cal(DRAMC_CTX_T *p,
 			return DRAM_OK;
 		}
 
-		mcSHOW_ERR_MSG(("[Error] Gating auto calibration fail!!\n"));
+		err("[Error] Gating auto calibration fail!!\n");
 	}
 
-	mcSHOW_DBG_MSG(("[Gating] SW mode calibration\n"));
+	msg("[Gating] SW mode calibration\n");
 
 	return dramc_rx_dqs_gating_sw_cal(p, use_enhanced_rdqs);
 }
@@ -5959,14 +5959,14 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
 
 	s1ChangeDQSINCTL = reg_TX_dly_DQSgated_min - u1TXDLY_Cal_min;
 
-	mcSHOW_DBG_MSG(("[RxdqsGatingPostProcess] freq %d\n"
+	msg("[RxdqsGatingPostProcess] freq %d\n"
 					"ChangeDQSINCTL %d, reg_TX_dly_DQSgated_min %d, u1TXDLY_Cal_min %d\n",
 						p->frequency,
-						s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min));
-	mcDUMP_REG_MSG(("[RxdqsGatingPostProcess] freq %d\n"
+						s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min);
+	reg_msg("[RxdqsGatingPostProcess] freq %d\n"
 					   "ChangeDQSINCTL %d, reg_TX_dly_DQSgated_min %d, u1TXDLY_Cal_min %d\n",
 						p->frequency,
-						s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min));
+						s1ChangeDQSINCTL, reg_TX_dly_DQSgated_min, u1TXDLY_Cal_min);
 
 	if (vGet_Div_Mode(p) == DIV16_MODE)
 		mck2ui_shift = 4;
@@ -5987,8 +5987,8 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
 
 		for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
 		{
-			mcSHOW_DBG_MSG2(("Rank: %d\n", u1RankIdx));
-			mcDUMP_REG_MSG(("Rank: %d\n", u1RankIdx));
+			msg2("Rank: %d\n", u1RankIdx);
+			reg_msg("Rank: %d\n", u1RankIdx);
 
 			for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++)
 			{
@@ -6032,13 +6032,13 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
 					ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] = ((u4ReadTXDLY_P1[u1RankIdx][dqs_i] & 0x1) << 2) + (ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i] & 0x3);
 				}
 #endif
-				mcSHOW_DBG_MSG(("best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i]));
-				mcDUMP_REG_MSG(("PostProcess best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i]));
+				msg("best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i]);
+				reg_msg("PostProcess best DQS%d dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_backup[u1RankIdx][dqs_i]);
 			}
 			for (dqs_i = 0; dqs_i < (p->data_width / DQS_BIT_NUMBER); dqs_i++)
 			{
-				mcSHOW_DBG_MSG(("best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i]));
-				mcDUMP_REG_MSG(("PostProcess best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i]));
+				msg("best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i]);
+				reg_msg("PostProcess best DQS%d P1 dly(2T, 0.5T) = (%d, %d)\n", dqs_i, ucbest_coarse_mck_P1_backup[u1RankIdx][dqs_i], ucbest_coarse_ui_P1_backup[u1RankIdx][dqs_i]);
 			}
 		}
 
@@ -6082,7 +6082,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
 
 	u4ReadDQSINCTL = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RK_DQSCTL),
 		MISC_SHU_RK_DQSCTL_DQSINCTL);
-	mcDUMP_REG_MSG(("u4ReadDQSINCTL=%d\n", u4ReadDQSINCTL));
+	reg_msg("u4ReadDQSINCTL=%d\n", u4ReadDQSINCTL);
 	u4ReadDQSINCTL -= s1ChangeDQSINCTL;
 
 	#if ENABLE_READ_DBI
@@ -6133,7 +6133,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
 	else
 	{
 		u4RankINCTL_ROOT = 0;
-		mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <2, Please check\n"));
+		err("u4RankINCTL_ROOT <2, Please check\n");
 #if (__ETT__)
 		while (1);
 #endif
@@ -6147,7 +6147,7 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
 	else
 	{
 		u4RankINCTL_ROOT = 0;
-		mcSHOW_ERR_MSG(("u4RankINCTL_ROOT <3, Risk for supporting 1066/RL8\n"));
+		err("u4RankINCTL_ROOT <3, Risk for supporting 1066/RL8\n");
 	}
 #endif
 
@@ -6175,9 +6175,9 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
 
 	u4XRTR2R = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIM_XRT), SHU_ACTIM_XRT_XRTR2R);
 
-	mcSHOW_DBG_MSG2(("TX_dly_DQSgated check: min %d  max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL));
-	mcSHOW_DBG_MSG2(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R));
-	mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R));
+	msg2("TX_dly_DQSgated check: min %d  max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL);
+	msg2("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R);
+	reg_msg("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R);
 #else
 	//XRTR2R=A-phy forbidden margin(6T) + reg_TX_dly_DQSgated (max) +Roundup(tDQSCKdiff/MCK+0.25MCK)+1(05T sel_ph margin)-1(forbidden margin overlap part)
 	//Roundup(tDQSCKdiff/MCK+1UI) =1~2 all LP3 and LP4 timing
@@ -6188,13 +6188,13 @@ void DramcRxdqsGatingPostProcess(DRAMC_CTX_T *p)
 	if (u4XRTR2R > 12)
 	{
 		u4XRTR2R = 12;
-		mcSHOW_ERR_MSG(("XRTR2R > 12, Max value is 12\n"));
+		err("XRTR2R > 12, Max value is 12\n");
 	}
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_ACTIM_XRT), u4XRTR2R, SHU_ACTIM_XRT_XRTR2R);
 
-	mcSHOW_DBG_MSG2(("TX_dly_DQSgated check: min %d  max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL));
-	mcSHOW_DBG_MSG2(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R));
-	mcDUMP_REG_MSG(("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R));
+	msg2("TX_dly_DQSgated check: min %d  max %d, ChangeDQSINCTL=%d\n", u1TXDLY_Cal_min, u1TXDLY_Cal_max, s1ChangeDQSINCTL);
+	msg2("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R);
+	reg_msg("DQSINCTL=%d, RANKINCTL=%d, u4XRTR2R=%d\n", u4ReadDQSINCTL, u4RankINCTL_ROOT, u4XRTR2R);
 #endif
 
 #if 0//ENABLE_RODT_TRACKING
@@ -6557,7 +6557,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 	// error handling
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context NULL\n"));
+		err("context NULL\n");
 		return DRAM_FAIL;
 	}
 
@@ -6665,7 +6665,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
 	if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE)))
 	{
-		mcSHOW_DBG_MSG(("[FAST_K] Bypass RX Calibration\n"));
+		msg("[FAST_K] Bypass RX Calibration\n");
 	}
 	else
 #endif
@@ -6678,11 +6678,11 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 #else
 		vPrintCalibrationBasicInfo(p);
 #endif
-		mcSHOW_DBG_MSG2(("Start DQ dly to find pass range UseTestEngine =%d\n", u1UseTestEngine));
+		msg2("Start DQ dly to find pass range UseTestEngine =%d\n", u1UseTestEngine);
 	}
 
-	mcSHOW_DBG_MSG2(("UseTestEngine: %d\n", u1UseTestEngine));
-	mcSHOW_DBG_MSG(("RX Vref Scan: %d\n", u1VrefScanEnable));
+	msg2("UseTestEngine: %d\n", u1UseTestEngine);
+	msg("RX Vref Scan: %d\n", u1VrefScanEnable);
 
 	if (u1VrefScanEnable)
 	{
@@ -6695,7 +6695,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 
 			if (u1UseTestEngine == PATTERN_TEST_ENGINE && ((u1KnownVref[0] == 0) || (u1KnownVref[1] == 0)))
 			{
-//				  mcSHOW_ERR_MSG(("\nWrong frequency K order= %d\n"));
+//				  err("\nWrong frequency K order= %d\n");
 				#if __ETT__
 				while (1);
 				#endif
@@ -6724,13 +6724,13 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 					u2VrefBegin = RX_VREF_RANGE_BEGIN_ODT_OFF;
 				}
 				u2VrefEnd = RX_VREF_RANGE_END-1;
-				mcSHOW_DBG_MSG(("\nSet Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd));
+				msg("\nSet Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd);
 			}
 			else
 			{
 				u2VrefBegin = 0;//Lewis@20160817: Enlarge RX Vref range for eye scan
 				u2VrefEnd = EYESCAN_RX_VREF_RANGE_END-1;
-				mcSHOW_DBG_MSG(("\nSet Eyescan Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd));
+				msg("\nSet Eyescan Vref Range= %d -> %d\n",u2VrefBegin,u2VrefEnd);
 			}
 		#endif
 		}
@@ -6805,8 +6805,8 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 
 			for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++)
 			{
-				mcSHOW_DBG_MSG(("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i));
-				mcDUMP_REG_MSG(("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i));
+				msg("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i);
+				reg_msg("\nFinal RX Vref Byte %d = %d to rank%d", u1ByteIdx, u2FinalVref[u1ByteIdx], rank_i);
 
 				gFinalRXVrefDQ[p->channel][rank_i][u1ByteIdx] = (U8) u2FinalVref[u1ByteIdx];
 				gFinalRXVrefDQForSpeedUp[p->channel][rank_i][p->odt_onoff][u1ByteIdx] = (U8) u2FinalVref[u1ByteIdx];
@@ -6821,10 +6821,10 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 	{
 		U32 u4B0Tatal =0;
 		U32 u4B1Tatal =0;
-		mcSHOW_DBG_MSG(("RX window per bit CH[%d] Rank[%d] window size\n", p->channel, p->rank));
+		msg("RX window per bit CH[%d] Rank[%d] window size\n", p->channel, p->rank);
 		for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx++)
 		{
-			mcSHOW_DBG_MSG(("DQ[%d] size = %d\n", u1BitIdx, gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]));
+			msg("DQ[%d] size = %d\n", u1BitIdx, gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx]);
 			if(u1BitIdx < 8)
 			{
 				u4B0Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx];
@@ -6834,7 +6834,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 				u4B1Tatal += gFinalRXPerbitWin[p->channel][p->rank][u1BitIdx];
 			}
 		}
-		mcSHOW_DBG_MSG(("total rx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal));
+		msg("total rx window size B0: %d B1: %d\n", u4B0Tatal, u4B1Tatal);
 	}
 #endif
 
@@ -6859,8 +6859,8 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 										P_Fld((U32)FinalWinPerBit[u1BitIdx + 8].best_dqdly, SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1) |
 										P_Fld((U32)FinalWinPerBit[u1BitIdx + 9].best_dqdly, SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1));
 
-		//mcSHOW_DBG_MSG(("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
-		//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly));
+		//msg("u1BitId %d  Addr 0x%2x = %2d %2d %2d %2d \n", u1BitIdx, DDRPHY_RXDQ1+u1BitIdx*2,
+		//				  FinalWinPerBit[u1BitIdx].best_dqdly, FinalWinPerBit[u1BitIdx+1].best_dqdly,  FinalWinPerBit[u1BitIdx+8].best_dqdly, FinalWinPerBit[u1BitIdx+9].best_dqdly);
 	}
 
 	DramPhyReset(p);
@@ -6874,39 +6874,39 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
 	vPrintCalibrationBasicInfo(p);
 
 #ifdef ETT_PRINT_FORMAT
-	mcSHOW_DBG_MSG(("DQS Delay:\nDQS0 = %d, DQS1 = %d\n"
+	msg("DQS Delay:\nDQS0 = %d, DQS1 = %d\n"
 					"DQM Delay:\nDQM0 = %d, DQM1 = %d\n",
 						iDQSDlyPerbyte[0], iDQSDlyPerbyte[1],
-						iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));
-	mcDUMP_REG_MSG(("DQS Delay:\nDQS0 = %d, DQS1 = %d\n"
+						iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]);
+	reg_msg("DQS Delay:\nDQS0 = %d, DQS1 = %d\n"
 					"DQM Delay:\nDQM0 = %d, DQM1 = %d\n",
 						iDQSDlyPerbyte[0], iDQSDlyPerbyte[1],
-						iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));
+						iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]);
 #else
-	mcSHOW_DBG_MSG(("DQS Delay:\nDQS0 = %2d, DQS1 = %2d\n"
+	msg("DQS Delay:\nDQS0 = %2d, DQS1 = %2d\n"
 					"DQM Delay:\nDQM0 = %2d, DQM1 = %2d\n",
 						iDQSDlyPerbyte[0], iDQSDlyPerbyte[1],
-						iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));
-	mcDUMP_REG_MSG(("DQS Delay:\nDQS0 = %2d, DQS1 = %2d\n"
+						iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]);
+	reg_msg("DQS Delay:\nDQS0 = %2d, DQS1 = %2d\n"
 					"DQM Delay:\nDQM0 = %2d, DQM1 = %2d\n",
 						iDQSDlyPerbyte[0], iDQSDlyPerbyte[1],
-						iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]));
+						iDQMDlyPerbyte[0], iDQMDlyPerbyte[1]);
 #endif
-	mcSHOW_DBG_MSG(("DQ Delay:\n"));
-	mcDUMP_REG_MSG(("DQ Delay:\n"));
+	msg("DQ Delay:\n");
+	reg_msg("DQ Delay:\n");
 
 	for (u1BitIdx = 0; u1BitIdx < p->data_width; u1BitIdx = u1BitIdx + 4)
 	{
 #ifdef ETT_PRINT_FORMAT
-		mcSHOW_DBG_MSG(("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly));
-		mcDUMP_REG_MSG(("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly));
+		msg("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly);
+		reg_msg("DQ%d =%d, DQ%d =%d, DQ%d =%d, DQ%d =%d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly);
 #else
-		mcSHOW_DBG_MSG(("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly));
-		mcDUMP_REG_MSG(("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly));
+		msg("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly);
+		reg_msg("DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d, DQ%2d =%2d\n", u1BitIdx, FinalWinPerBit[u1BitIdx].best_dqdly, u1BitIdx+1, FinalWinPerBit[u1BitIdx+1].best_dqdly, u1BitIdx+2, FinalWinPerBit[u1BitIdx+2].best_dqdly, u1BitIdx+3, FinalWinPerBit[u1BitIdx+3].best_dqdly);
 #endif
 	}
-	mcSHOW_DBG_MSG(("\n\n"));
-	mcSHOW_DBG_MSG3(("[DramcRxWindowPerbitCal] Done\n"));
+	msg("\n\n");
+	msg3("[DramcRxWindowPerbitCal] Done\n");
 
 	#if LP5_DDR4266_RDBI_WORKAROUND
 	if((is_lp5_family(p)) && (p->frequency >= 2133))
@@ -6999,7 +6999,7 @@ static U8 DramcRxDVSCal(DRAMC_CTX_T *p, U8 u1byte)
 		u1falling_lag = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_FT_STATUS1), MISC_FT_STATUS1_AD_RX_ARDQ_DVS_F_LAG_B1);
 	}
 
-	mcSHOW_DBG_MSG2(("Byte%d | LEAD(%d %d) | LAG(%d %d)\n", u1byte, u1rising_lead, u1falling_lead, u1rising_lag, u1falling_lag));
+	msg2("Byte%d | LEAD(%d %d) | LAG(%d %d)\n", u1byte, u1rising_lead, u1falling_lead, u1rising_lag, u1falling_lag);
 
 	u1lead_lag = (u1rising_lead | u1falling_lead | u1rising_lag | u1falling_lag);
 
@@ -7029,11 +7029,11 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
 	// error handling
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context NULL\n"));
+		err("context NULL\n");
 		return DRAM_FAIL;
 	}
 
-	mcSHOW_DBG_MSG(("\\\RX DVS calibration\\\\n"));
+	msg("\\\RX DVS calibration\\\\n");
 
 	//When doing RxWindowPerbitCal, should make sure that auto refresh is disable
 	vAutoRefreshSwitch(p, DISABLE);
@@ -7071,7 +7071,7 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
 	S16DelayBegin = -80;
 	u16DelayEnd = 100;
 
-	mcSHOW_DBG_MSG(("\nRX Delay %d -> %d, step: %d\n", S16DelayBegin, u16DelayEnd, u16DelayStep));
+	msg("\nRX Delay %d -> %d, step: %d\n", S16DelayBegin, u16DelayEnd, u16DelayStep);
 
 	{
 		// Adjust DQM output delay to 0
@@ -7094,7 +7094,7 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
 
 				u4err_value = DramcEngine2Run(p, TE_OP_WRITE_READ_CHECK, p->test_pattern);
 
-				mcSHOW_DBG_MSG2(("iDelay= %4d, err_value: 0x%x", iDelay, u4err_value));
+				msg2("iDelay= %4d, err_value: 0x%x", iDelay, u4err_value);
 
 				for(u1ByteIdx=0; u1ByteIdx<(p->data_width/DQS_BIT_NUMBER); u1ByteIdx++)
 				{
@@ -7104,7 +7104,7 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
 					{
 						u1DVS_first_pass[u1ByteIdx] = iDelay;
 						u1DVS_first_flag[u1ByteIdx] = 1;
-						mcSHOW_DBG_MSG(("Byte%d find first pass delay\n"))
+						msg("Byte%d find first pass delay\n")
 					}
 					else if (((u1lead_lag == 1) || (((u4err_value >> (u1ByteIdx<<3)) & 0xff) != 0)) && (u1DVS_first_flag[u1ByteIdx] == 1) && (u1finish_flag[u1ByteIdx] == 0))
 					{
@@ -7114,19 +7114,19 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
 						{
 							u1DVS_pass_window[u1ByteIdx] = 0;
 							u1DVS_first_flag[u1ByteIdx] = 0;
-							mcSHOW_DBG_MSG(("Byte%d find fake window\n"))
+							msg("Byte%d find fake window\n")
 						}
 						else
 						{
 							 u1finish_flag[u1ByteIdx] = 1;
-							 mcSHOW_DBG_MSG(("Byte%d find pass window\n"))
+							 msg("Byte%d find pass window\n")
 						}
 					}
 				}
 
 				if ((u1finish_flag[0]==1) && (u1finish_flag[1]==1))
 				{
-					mcSHOW_DBG_MSG(("Two byte DVS window find, early break!\n"));
+					msg("Two byte DVS window find, early break!\n");
 					break;
 				}
 			}
@@ -7138,7 +7138,7 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
 	for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++)
 	{
 		u1DVS_increase[p->rank][u1ByteIdx] = (u1DVS_pass_window[u1ByteIdx] > 8)? ((u1DVS_pass_window[u1ByteIdx] - 8) >> 3): 0;
-		mcSHOW_DBG_MSG(("\nByte %d final DVS window size(M) %d, DVS increase %d\n", u1ByteIdx, u1DVS_pass_window[u1ByteIdx], u1DVS_increase[p->rank][u1ByteIdx]));
+		msg("\nByte %d final DVS window size(M) %d, DVS increase %d\n", u1ByteIdx, u1DVS_pass_window[u1ByteIdx], u1DVS_increase[p->rank][u1ByteIdx]);
 	}
 
 	DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress) / sizeof(U32));
@@ -7149,8 +7149,8 @@ DRAM_STATUS_T DramcRxDVSWindowCal(DRAMC_CTX_T *p)
 
 	vPrintCalibrationBasicInfo(p);
 
-	mcSHOW_DBG_MSG(("\n\n"));
-	mcSHOW_DBG_MSG3(("[DramcRxDVSWindowCal] Done\n"));
+	msg("\n\n");
+	msg3("[DramcRxDVSWindowCal] Done\n");
 
 return DRAM_OK;
 }
@@ -7177,7 +7177,7 @@ void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p)
 			u1DVS_dly_final[u1ByteIdx] = u1DVS_increase_final + (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1));
 			vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B1_DQ11), u1DVS_dly_final[u1ByteIdx], SHU_B1_DQ11_RG_RX_ARDQ_DVS_DLY_B1);
 		}
-		mcSHOW_DBG_MSG(("Byte%d final DVS delay: %d\n", u1ByteIdx, u1DVS_dly_final[u1ByteIdx]));
+		msg("Byte%d final DVS delay: %d\n", u1ByteIdx, u1DVS_dly_final[u1ByteIdx]);
 	}
 
 	for(rank_i=RANK_0; rank_i< p->support_rank_num; rank_i++)
@@ -7188,7 +7188,7 @@ void DramcDramcRxDVSCalPostProcess(DRAMC_CTX_T *p)
 
 	if ((DramcRxDVSCal(p, 0) == 1) || (DramcRxDVSCal(p, 1) == 1)) //Prevent set wrong DV dly
 	{
-		mcSHOW_ERR_MSG(("Final DVS delay is out of RX window\n"));
+		err("Final DVS delay is out of RX window\n");
 		for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++)
 		{
 			if (u1DVS_dly_final[u1ByteIdx] > 0)
@@ -7240,7 +7240,7 @@ static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val)
 			u1DATLAT_DSEL = curr_val - 1;
 	}
 
-//	  mcSHOW_DBG_MSG(("DATLAT: %d, u1DATLAT_DSEL: %d\n", curr_val, u1DATLAT_DSEL));
+//	  msg("DATLAT: %d, u1DATLAT_DSEL: %d\n", curr_val, u1DATLAT_DSEL);
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT),
 			P_Fld(curr_val, MISC_SHU_RDAT_DATLAT) |
@@ -7254,7 +7254,7 @@ static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val)
 	u1DLECG_OptionEXT1 = (curr_val >= 8)? (1): (0);
 	u1DLECG_OptionEXT2 = (curr_val >= 14)? (1): (0);
 	u1DLECG_OptionEXT3 = (curr_val >= 19)? (1): (0);
-//	  mcSHOW_DBG_MSG(("u1DLECG_OptionEXT1: %d, 2 for %d, 3 for %d\n", u1DLECG_OptionEXT1, u1DLECG_OptionEXT2, u1DLECG_OptionEXT3));
+//	  msg("u1DLECG_OptionEXT1: %d, 2 for %d, 3 for %d\n", u1DLECG_OptionEXT1, u1DLECG_OptionEXT2, u1DLECG_OptionEXT3);
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHU_RX_CG_SET0),
 			P_Fld(u1DLECG_OptionEXT1, SHU_RX_CG_SET0_READ_START_EXTEND1) |
 			P_Fld(u1DLECG_OptionEXT1, SHU_RX_CG_SET0_DLE_LAST_EXTEND1) |
@@ -7277,12 +7277,12 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
 	// error handling
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context NULL\n"));
+		err("context NULL\n");
 		return DRAM_FAIL;
 	}
 
-	mcSHOW_DBG_MSG(("\n[DATLAT]\n"
-					"Freq=%d, CH%d RK%d\n\n", p->frequency, p->channel, p->rank));
+	msg("\n[DATLAT]\n"
+					"Freq=%d, CH%d RK%d\n\n", p->frequency, p->channel, p->rank);
 
 	// pre-save
 	// 0x07c[6:4]	DATLAT bit2-bit0
@@ -7293,8 +7293,8 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
 
 	// init best_step to default
 	ucbest_step = (U8) u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT), MISC_SHU_RDAT_DATLAT);
-	mcSHOW_DBG_MSG(("DATLAT Default: 0x%x\n", ucbest_step));
-	mcDUMP_REG_MSG(("DATLAT Default: 0x%x\n", ucbest_step));
+	msg("DATLAT Default: 0x%x\n", ucbest_step);
+	reg_msg("DATLAT Default: 0x%x\n", ucbest_step);
 
 	// 1.set DATLAT 0-15 (0-21 for MT6595)
 	// 2.enable engine1 or engine2
@@ -7318,19 +7318,19 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
 
 	aru1RxDatlatResult[p->rank] = ucbest_step;
 
-	mcSHOW_DBG_MSG(("best_step = %d\n\n", ucbest_step));
-	mcDUMP_REG_MSG(("best_step=%d\n\n", ucbest_step));
+	msg("best_step = %d\n\n", ucbest_step);
+	reg_msg("best_step=%d\n\n", ucbest_step);
 
 #if __A60868_TO_BE_PORTING__
 #if __ETT__
 	U8 _init_Datlat_value = vDramcACTimingGetDatLat(p);
 	if ((_init_Datlat_value > (ucbest_step + 1)) || (_init_Datlat_value < (ucbest_step - 1)))
 	{
-		mcSHOW_DBG_MSG(("[WARNING!!] Datlat initial value(%d) = best_step(%d) %c %d, out of range!\n\n",
+		msg("[WARNING!!] Datlat initial value(%d) = best_step(%d) %c %d, out of range!\n\n",
 						   _init_Datlat_value,
 						   ucbest_step,
 						   (ucbest_step > _init_Datlat_value)? '-': '+',
-						   abs(ucbest_step - _init_Datlat_value)));
+						   abs(ucbest_step - _init_Datlat_value));
 		while (1);
 	}
 #endif
@@ -7348,7 +7348,7 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
 	}
 #endif
 
-	mcSHOW_DBG_MSG3(("[DramcRxdatlatCal] Done\n"));
+	msg3("[DramcRxdatlatCal] Done\n");
 	return DRAM_OK;
 }
 
@@ -7388,7 +7388,7 @@ DRAM_STATUS_T DramcDualRankRxdatlatCal(DRAMC_CTX_T *p)
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_RDSEL_TRACK), u1FinalDatlat, SHU_MISC_RDSEL_TRACK_DMDATLAT_I);
 #endif
 
-	mcSHOW_DBG_MSG(("[DualRankRxdatlatCal] RK0: %d, RK1: %d, Final_Datlat %d\n", u1Datlat0, u1Datlat1, u1FinalDatlat));
+	msg("[DualRankRxdatlatCal] RK0: %d, RK1: %d, Final_Datlat %d\n", u1Datlat0, u1Datlat1, u1FinalDatlat);
 
 	return DRAM_OK;
 
@@ -7627,7 +7627,7 @@ static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca
 		if (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)] > 0)
 		{
 			U16 u2TmpShift;
-			mcSHOW_DBG_MSG(("TX_TDQS2DQ_PRE_CAL : change DQ begin %d -->", u2DQDelayBegin));
+			msg("TX_TDQS2DQ_PRE_CAL : change DQ begin %d -->", u2DQDelayBegin);
 
 			u2TmpShift = (u2DQS2DQ_Pre_Cal[p->channel][p->rank][vGet_Div_Mode(p)]* p->frequency) / 1000;
 			if (u2TmpShift >= 15)
@@ -7636,7 +7636,7 @@ static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca
 				u2TmpShift = 0;
 
 			u2DQDelayBegin += u2TmpShift;
-			mcSHOW_DBG_MSG(("%d (+%d)\n", u2DQDelayBegin, u2TmpShift));
+			msg("%d (+%d)\n", u2DQDelayBegin, u2TmpShift);
 		}
 	}
 	#endif
@@ -7667,7 +7667,7 @@ static void TXScanRange_PI(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION_TYTE_T ca
 	*pu2End = u2DQDelayEnd;
 
 	#if 0//TX_TDQS2DQ_PRE_CAL
-	mcSHOW_DBG_MSG(("TXScanRange_PI %d~%d\n", u2DQDelayBegin, u2DQDelayEnd));
+	msg("TXScanRange_PI %d~%d\n", u2DQDelayBegin, u2DQDelayEnd);
 	#endif
 }
 
@@ -7708,11 +7708,11 @@ static U16 TxChooseVref(DRAMC_CTX_T *p, PASS_WIN_DATA_BY_VREF_T pVrefInfo[], U8
 
 	for (u1VrefIdx = 0; u1VrefIdx < u1VrefNum; u1VrefIdx++)
 	{
-		mcSHOW_DBG_MSG(("TX Vref=%d, minBit %d, minWin=%d, winSum=%d\n",
+		msg("TX Vref=%d, minBit %d, minWin=%d, winSum=%d\n",
 			pVrefInfo[u1VrefIdx].u2VrefUsed,
 			pVrefInfo[u1VrefIdx].u1WorseBitIdx_byVref,
 			pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref,
-			pVrefInfo[u1VrefIdx].u2WinSum_byVref));
+			pVrefInfo[u1VrefIdx].u2WinSum_byVref);
 
 		#if LP4_TX_VREF_PASS_CONDITION
 		if ((pVrefInfo[u1VrefIdx].u1WorseBitWinSize_byVref > LP4_TX_VREF_PASS_CONDITION))
@@ -7761,7 +7761,7 @@ static U16 TxChooseVref(DRAMC_CTX_T *p, PASS_WIN_DATA_BY_VREF_T pVrefInfo[], U8
 	{
 		// vref pass window found
 		u2FinalVref = (u1VrefPassBegin_Final + u1VrefPassEnd_Final) >> 1;
-		mcSHOW_DBG_MSG(("[TxChooseVref] Window > %d, Vref (%d~%d), Final Vref %d\n", LP4_TX_VREF_PASS_CONDITION, u1VrefPassBegin_Final, u1VrefPassEnd_Final, u2FinalVref));
+		msg("[TxChooseVref] Window > %d, Vref (%d~%d), Final Vref %d\n", LP4_TX_VREF_PASS_CONDITION, u1VrefPassBegin_Final, u1VrefPassEnd_Final, u2FinalVref);
 	}
 	else
 	#endif
@@ -7779,7 +7779,7 @@ static U16 TxChooseVref(DRAMC_CTX_T *p, PASS_WIN_DATA_BY_VREF_T pVrefInfo[], U8
 			}
 		}
 
-		mcSHOW_DBG_MSG(("[TxChooseVref] Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", u1WorseBitIdx, u1WinSizeOfWorseBit, u2MaxWinSum, u2FinalVref));
+		msg("[TxChooseVref] Worse bit %d, Min win %d, Win sum %d, Final Vref %d\n", u1WorseBitIdx, u1WinSizeOfWorseBit, u2MaxWinSum, u2FinalVref);
 	}
 
 	return u2FinalVref;
@@ -7807,7 +7807,7 @@ static void DramcTXSetVref(DRAMC_CTX_T *p, U8 u1VrefRange, U8 u1VrefValue)
 #endif
 
 	#if CALIBRATION_SPEED_UP_DEBUG
-	mcSHOW_DBG_MSG(("Yulia TX Vref : CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u1VrefRange, (u1VrefValue & 0x3f)));
+	msg("Yulia TX Vref : CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u1VrefRange, (u1VrefValue & 0x3f));
 	#endif
 }
 
@@ -7821,13 +7821,13 @@ static void TXSetFinalVref(DRAMC_CTX_T *p, U16 u2FinalRange, U16 u2FinalVref)
 #endif
 
 #if VENDER_JV_LOG
-	mcSHOW_DBG_MSG5(("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref));
+	msg5("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref);
 #else
-	mcSHOW_DBG_MSG(("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref));
+	msg("\nFinal TX Range %d Vref %d\n\n", u2FinalRange, u2FinalVref);
 #endif
 
 	#if CALIBRATION_SPEED_UP_DEBUG
-	mcSHOW_DBG_MSG(("Yulia TX Vref Final: CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u2FinalRange, u2FinalVref));
+	msg("Yulia TX Vref Final: CH%d Rank%d, TX Range %d Vref %d\n\n", p->channel, p->rank, u2FinalRange, u2FinalVref);
 	#endif
 }
 
@@ -8029,10 +8029,10 @@ static void Tx_Auto_K_complete_check(DRAMC_CTX_T *p)
 	{
 		mcDELAY_US(1);
 		u4loop_count++;
-		//mcSHOW_DBG_MSG(("Wait! TX auto K is not done!\n"));
+		//msg("Wait! TX auto K is not done!\n");
 		if (u4loop_count > 100000)
 		{
-			mcSHOW_ERR_MSG(("Error! TX auto K is not done!\n"));
+			err("Error! TX auto K is not done!\n");
 			break;
 		}
 	}
@@ -8040,11 +8040,11 @@ static void Tx_Auto_K_complete_check(DRAMC_CTX_T *p)
 	if ((u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_RESULT8), TX_ATK_RESULT8_TX_ATK_FIND_PW) == 0x1))
 	{
 		vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK);
-		mcSHOW_DBG_MSG(("Tx auto K, all bit find passs window\n"));
+		msg("Tx auto K, all bit find passs window\n");
 	}
 	else
 	{
-		mcSHOW_ERR_MSG(("Error! TX auto K is fail!\n"));
+		err("Error! TX auto K is fail!\n");
 	}
 }
 
@@ -8107,11 +8107,11 @@ static void Tx_Auto_K_Debug_Message(DRAMC_CTX_T *p, U8 u1PI_Len)
 		u4status_bit[3][u1BitIdx] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TX_ATK_DBG_BIT_STATUS4));
 	}
 
-	mcSHOW_DBG_MSG2(("Debug TX DQ PASS/FAIL status:\n"));
+	msg2("Debug TX DQ PASS/FAIL status:\n");
 
 	for (u2Length = 0; u2Length < u2Length_max; u2Length++)
 	{
-		mcSHOW_DBG_MSG2(("Delay=%3d ", u2Length));
+		msg2("Delay=%3d ", u2Length);
 
 		for (u1bit_num = 0; u1bit_num < p->data_width; u1bit_num++)
 		{
@@ -8119,21 +8119,21 @@ static void Tx_Auto_K_Debug_Message(DRAMC_CTX_T *p, U8 u1PI_Len)
 
 			if (u4status == 0)
 			{
-				mcSHOW_DBG_MSG2(("x"));
+				msg2("x");
 			}
 			else
 			{
-				mcSHOW_DBG_MSG2(("o"));
+				msg2("o");
 			}
 
 			if (u1bit_num == (p->data_width - 1))
 			{
-				mcSHOW_DBG_MSG2((" \n"));
+				msg2(" \n");
 			}
 		}
 	}
 
-	//mcSHOW_DBG_MSG(("Debug DQ PASS(1)/FAIL(0) bit: %d, STATUS1: 0x%x, STATUS2: 0x%x, STATUS3: 0x%x, STATUS4: 0x%x,\n",u1BitIdx,u4status_bit[0][u1BitIdx],u4status_bit[1][u1BitIdx],u4status_bit[2][u1BitIdx],u4status_bit[3][u1BitIdx]));
+	//msg("Debug DQ PASS(1)/FAIL(0) bit: %d, STATUS1: 0x%x, STATUS2: 0x%x, STATUS3: 0x%x, STATUS4: 0x%x,\n",u1BitIdx,u4status_bit[0][u1BitIdx],u4status_bit[1][u1BitIdx],u4status_bit[2][u1BitIdx],u4status_bit[3][u1BitIdx]);
 }
 #endif
 #endif
@@ -8195,7 +8195,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context NULL\n"));
+		err("context NULL\n");
 		return DRAM_FAIL;
 	}
 
@@ -8280,7 +8280,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 	if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
 	{
 		TXSetDelayReg_DQ(p, u1UpdateRegUI, ucdq_reg_ui_large, ucdq_reg_oen_ui_large, ucdq_reg_ui_small, ucdq_reg_oen_ui_small, ucdq_reg_pi);
-		mcSHOW_DBG_MSG(("TX Auto-K set begin delay DQ MCK: %d, UI: %d, PI: %d\n", ucdq_reg_ui_large[0], ucdq_reg_ui_small[0], ucdq_reg_pi[0]));
+		msg("TX Auto-K set begin delay DQ MCK: %d, UI: %d, PI: %d\n", ucdq_reg_ui_large[0], ucdq_reg_ui_small[0], ucdq_reg_pi[0]);
 
 		#if TX_AUTO_K_WORKAROUND
 		if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (u1backup_Rank == 1))
@@ -8290,7 +8290,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 	if (calType == TX_DQ_DQS_MOVE_DQM_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
 	{
 		TXSetDelayReg_DQM(p, u1UpdateRegUI, ucdq_reg_dqm_ui_large, ucdq_reg_dqm_oen_ui_large, ucdq_reg_dqm_ui_small, ucdq_reg_dqm_oen_ui_small, ucdq_reg_dqm_pi);
-		mcSHOW_DBG_MSG(("TX Auto-K set begin delay DQM MCK: %d, UI: %d, PI: %d\n", ucdq_reg_dqm_ui_large[0], ucdq_reg_dqm_ui_small[0], ucdq_reg_dqm_pi[0]));
+		msg("TX Auto-K set begin delay DQM MCK: %d, UI: %d, PI: %d\n", ucdq_reg_dqm_ui_large[0], ucdq_reg_dqm_ui_small[0], ucdq_reg_dqm_pi[0]);
 
 		#if TX_AUTO_K_WORKAROUND
 		if ((calType == TX_DQ_DQS_MOVE_DQM_ONLY) && (u1backup_Rank == 1))
@@ -8324,9 +8324,9 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 	}
 
 #if 0
-	mcSHOW_DBG_MSG(("[TxWindowPerbitCal] calType=%d, VrefScanEnable %d (Range %d,  VrefBegin %d, u2VrefEnd %d)\n"
+	msg("[TxWindowPerbitCal] calType=%d, VrefScanEnable %d (Range %d,  VrefBegin %d, u2VrefEnd %d)\n"
 					"\nBegin, DQ Scan Range %d~%d\n",
-					calType, u1VrefScanEnable, u2FinalRange, u2VrefBegin, u2VrefEnd, u2DQDelayBegin, u2DQDelayEnd));
+					calType, u1VrefScanEnable, u2FinalRange, u2VrefBegin, u2VrefEnd, u2DQDelayBegin, u2DQDelayEnd);
 #endif
 
 	#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
@@ -8360,13 +8360,13 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 			if (u1VrefScanEnable)
 			{
 				#if (!REDUCE_LOG_FOR_PRELOADER)
-				mcSHOW_DBG_MSG(("\n\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel));
+				msg("\n\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel);
 				#endif
 
 				#if VENDER_JV_LOG
 				if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
 				{
-					mcSHOW_DBG_MSG5(("\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel));
+					msg5("\n\tLP4 TX VrefRange %d, VrefLevel=%d\n", u2FinalRange, u2VrefLevel);
 				}
 				#endif
 
@@ -8374,7 +8374,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 			}
 			else
 			{
-				mcSHOW_DBG_MSG(("\n\n\tTX Vref Scan disable\n"));
+				msg("\n\n\tTX Vref Scan disable\n");
 			}
 
 			// initialize parameters
@@ -8464,14 +8464,14 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 
 				if (u1VrefScanEnable == 0 && (calType != TX_DQ_DQS_MOVE_DQM_ONLY))
 				{
-					//mcSHOW_DBG_MSG(("Delay=%3d |%2d %2d %3d| %2d %2d| 0x%8x [0]",uiDelay, ucdq_ui_large,ucdq_ui_small, ucdq_pi, ucdq_oen_ui_large,ucdq_oen_ui_small, u4err_value));
+					//msg("Delay=%3d |%2d %2d %3d| %2d %2d| 0x%8x [0]",uiDelay, ucdq_ui_large,ucdq_ui_small, ucdq_pi, ucdq_oen_ui_large,ucdq_oen_ui_small, u4err_value);
 					#ifdef ETT_PRINT_FORMAT
 					if (u4err_value != 0)
 					{
-						mcSHOW_DBG_MSG2(("%d |%d %d %d|[0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi));
+						msg2("%d |%d %d %d|[0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi);
 					}
 					#else
-					mcSHOW_DBG_MSG2(("Delay=%3d |%2d %2d %3d| 0x%8x [0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi, u4err_value));
+					msg2("Delay=%3d |%2d %2d %3d| 0x%8x [0]", uiDelay, ucdq_ui_large, ucdq_ui_small, ucdq_pi, u4err_value);
 					#endif
 				}
 
@@ -8486,16 +8486,16 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 						{
 							if (u1BitIdx % DQS_BIT_NUMBER == 0)
 							{
-								mcSHOW_DBG_MSG2((" "));
+								msg2(" ");
 							}
 
 							if (u4fail_bit == 0)
 							{
-								 mcSHOW_DBG_MSG2(("o"));
+								 msg2("o");
 							}
 							else
 							{
-								mcSHOW_DBG_MSG2(("x"));
+								msg2("x");
 							}
 						}
 					}
@@ -8516,7 +8516,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 
 								if (uiDelay == u2DQDelayBegin)
 								{
-									mcSHOW_ERR_MSG(("TX_TDQS2DQ_PRE_CAL: Warning, possible miss TX window boundary\n"));
+									err("TX_TDQS2DQ_PRE_CAL: Warning, possible miss TX window boundary\n");
 									#if __ETT__
 									while (1);
 									#endif
@@ -8542,8 +8542,8 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 							{
 								if ((VrefWinPerBit[u1BitIdx].last_pass != PASS_RANGE_NA) && (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass) > 0)
 								{
-									mcSHOW_DBG_MSG2(("Bit[%d] Bigger window update %d > %d, window broken?\n", u1BitIdx, \
-										(WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass), (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass)));
+									msg2("Bit[%d] Bigger window update %d > %d, window broken?\n", u1BitIdx, \
+										(WinPerBit[u1BitIdx].last_pass - WinPerBit[u1BitIdx].first_pass), (VrefWinPerBit[u1BitIdx].last_pass - VrefWinPerBit[u1BitIdx].first_pass));
 								}
 
 								//if window size bigger than TX_PASS_WIN_CRITERIA, consider as real pass window. If not, don't update finish counte and won't do early break;
@@ -8566,7 +8566,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 				{
 					if(u4err_value != 0)
 					{
-						mcSHOW_DBG_MSG2((" [MSB]\n"));
+						msg2(" [MSB]\n");
 					}
 				}
 
@@ -8576,9 +8576,9 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 					vSetCalibrationResult(p, DRAM_CALIBRATION_TX_PERBIT, DRAM_OK);
 					#if !REDUCE_LOG_FOR_PRELOADER
 					#ifdef ETT_PRINT_FORMAT
-					mcSHOW_DBG_MSG2(("TX calibration finding left boundary early break. PI DQ delay=0x%B\n", uiDelay));
+					msg2("TX calibration finding left boundary early break. PI DQ delay=0x%B\n", uiDelay);
 					#else
-					mcSHOW_DBG_MSG2(("TX calibration finding left boundary early break. PI DQ delay=0x%2x\n", uiDelay));
+					msg2("TX calibration finding left boundary early break. PI DQ delay=0x%2x\n", uiDelay);
 					#endif
 					#endif
 					break;	//early break
@@ -8618,10 +8618,10 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 
 				if ((VrefWinPerBit[u1BitIdx].first_pass == (int)(u2DQDelayBegin - ucdq_pi)) || (VrefWinPerBit[u1BitIdx].last_pass == (int)(u2DQDelayBegin + u4Length)))
 				{
-					mcSHOW_ERR_MSG(("Error! Probably miss pass window!\n"));
+					err("Error! Probably miss pass window!\n");
 				}
 
-				mcSHOW_DBG_MSG(("TX DQ bit %d, first pass: %d, last pass: %d\n", u1BitIdx, VrefWinPerBit[u1BitIdx].first_pass, VrefWinPerBit[u1BitIdx].last_pass));
+				msg("TX DQ bit %d, first pass: %d, last pass: %d\n", u1BitIdx, VrefWinPerBit[u1BitIdx].first_pass, VrefWinPerBit[u1BitIdx].last_pass);
 				#else
 				//if(VrefWinPerBit[u1BitIdx].last_pass == VrefWinPerBit[u1BitIdx].first_pass)
 				if (VrefWinPerBit[u1BitIdx].first_pass == PASS_RANGE_NA)
@@ -8649,7 +8649,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 				#if VENDER_JV_LOG
 				if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
 				{
-					mcSHOW_DBG_MSG5(("TX Bit%d, %d%%\n", u1BitIdx, (VrefWinPerBit[u1BitIdx].win_size * 100 + 31) / 32));
+					msg5("TX Bit%d, %d%%\n", u1BitIdx, (VrefWinPerBit[u1BitIdx].win_size * 100 + 31) / 32);
 				}
 				#endif
 
@@ -8665,7 +8665,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 			#if __ETT__
 			if (u1VrefScanEnable == 0)
 			{
-				//mcSHOW_DBG_MSG(("\n\tCH=%d, VrefRange= %d, VrefLevel = %d\n", p->channel, u2FinalRange, u2VrefLevel));
+				//msg("\n\tCH=%d, VrefRange= %d, VrefLevel = %d\n", p->channel, u2FinalRange, u2VrefLevel);
 				TxPrintWidnowInfo(p, VrefWinPerBit);
 			}
 			#endif
@@ -8693,7 +8693,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 			if (u1VrefScanEnable && (u2TempWinSum < (u2MaxWindowSum * 95 / 100)) && (u1min_winsize > TX_PASS_WIN_CRITERIA))
 			#endif
 			{
-				mcSHOW_DBG_MSG(("\nTX Vref early break, caculate TX vref\n"));
+				msg("\nTX Vref early break, caculate TX vref\n");
 				break;
 			}
 
@@ -8771,7 +8771,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 		gFinalTXPerbitWin_min_max[p->channel][p->rank] = u1min_winsize;
 		if(u1min_winsize<16)
 		{
-			mcSHOW_ERR_MSG(("[WARNING] Smaller TX win !!\n"));
+			err("[WARNING] Smaller TX win !!\n");
 			#if CHECK_HQA_CRITERIA
 			while(1);
 			#endif
@@ -8784,14 +8784,14 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 	if ((calType == TX_DQ_DQS_MOVE_DQ_ONLY) && (p->frequency >= 1333) && (p->u2DelayCellTimex100 != 0))
 	{
 		u1EnableDelayCell = 1;
-		mcSHOW_DBG_MSG(("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", p->u2DelayCellTimex100));
+		msg("[TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =%d/100 ps\n", p->u2DelayCellTimex100);
 	}
 
 	//Calculate the center of DQ pass window
 	//average the center delay
 	for (u1ByteIdx = 0; u1ByteIdx < (p->data_width / DQS_BIT_NUMBER); u1ByteIdx++)
 	{
-		mcSHOW_DBG_MSG((" == TX Byte %d ==\n", u1ByteIdx));
+		msg(" == TX Byte %d ==\n", u1ByteIdx);
 		u2DQM_Delay = ((u2Center_min[u1ByteIdx] + u2Center_max[u1ByteIdx]) >> 1); //(max +min)/2
 
 		if (u1EnableDelayCell == 0)
@@ -8811,17 +8811,17 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 				{
 					u2DelayCellOfst[u1BitTemp] = (u1PIDiff * 100000000 / (p->frequency << 6)) / p->u2DelayCellTimex100;
 
-					mcSHOW_DBG_MSG(("u2DelayCellOfst[%d]=%d cells (%d PI)\n", u1BitTemp, u2DelayCellOfst[u1BitTemp], u1PIDiff));
+					msg("u2DelayCellOfst[%d]=%d cells (%d PI)\n", u1BitTemp, u2DelayCellOfst[u1BitTemp], u1PIDiff);
 
 					if(u2DelayCellOfst[u1BitTemp]>255)
 					{
-						mcSHOW_DBG_MSG(("[WARNING] TX DQ%d delay cell %d >255, adjust to 255 cell\n", u1BitIdx, u2DelayCellOfst[u1BitTemp]));
+						msg("[WARNING] TX DQ%d delay cell %d >255, adjust to 255 cell\n", u1BitIdx, u2DelayCellOfst[u1BitTemp]);
 						u2DelayCellOfst[u1BitTemp] =255;
 					}
 				}
 				else
 				{
-					mcSHOW_ERR_MSG(("Error: Cell time (p->u2DelayCellTimex100) is 0 \n"));
+					err("Error: Cell time (p->u2DelayCellTimex100) is 0 \n");
 					break;
 				}
 			}
@@ -8836,18 +8836,18 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 
 		if (calType == TX_DQ_DQS_MOVE_DQ_ONLY || calType == TX_DQ_DQS_MOVE_DQ_DQM)
 		{
-			mcSHOW_DBG_MSG(("Update DQ	dly =%d (%d ,%d, %d)  DQ  OEN =(%d ,%d)\n",
+			msg("Update DQ	dly =%d (%d ,%d, %d)  DQ  OEN =(%d ,%d)\n",
 							uiDelay, ucdq_reg_ui_large[u1ByteIdx], ucdq_reg_ui_small[u1ByteIdx], ucdq_reg_pi[u1ByteIdx], \
-							ucdq_reg_oen_ui_large[u1ByteIdx], ucdq_reg_oen_ui_small[u1ByteIdx]));
+							ucdq_reg_oen_ui_large[u1ByteIdx], ucdq_reg_oen_ui_small[u1ByteIdx]);
 		}
 
 		//if(calType ==TX_DQ_DQS_MOVE_DQM_ONLY || calType== TX_DQ_DQS_MOVE_DQ_DQM)
 		{
-			mcSHOW_DBG_MSG(("Update DQM dly =%d (%d ,%d, %d)  DQM OEN =(%d ,%d)",
+			msg("Update DQM dly =%d (%d ,%d, %d)  DQM OEN =(%d ,%d)",
 					u2DQM_Delay, ucdq_reg_dqm_ui_large[u1ByteIdx], ucdq_reg_dqm_ui_small[u1ByteIdx], ucdq_reg_dqm_pi[u1ByteIdx], \
-					ucdq_reg_dqm_oen_ui_large[u1ByteIdx], ucdq_reg_dqm_oen_ui_small[u1ByteIdx]));
+					ucdq_reg_dqm_oen_ui_large[u1ByteIdx], ucdq_reg_dqm_oen_ui_small[u1ByteIdx]);
 		}
-		mcSHOW_DBG_MSG(("\n"));
+		msg("\n");
 
 #ifdef FOR_HQA_REPORT_USED
 		if (calType == TX_DQ_DQS_MOVE_DQ_ONLY)
@@ -8950,7 +8950,7 @@ DRAM_STATUS_T DramcTxWindowPerbitCal(DRAMC_CTX_T *p, DRAM_TX_PER_BIT_CALIBRATION
 	}
 #endif
 
-	mcSHOW_DBG_MSG3(("[TxWindowPerbitCal] Done\n\n"));
+	msg3("[TxWindowPerbitCal] Done\n\n");
 
 	#if 0
 	vIO32WriteFldAlign_All(DRAMC_REG_ADDR(DRAMC_REG_PADCTL4), 1, PADCTL4_CKEFIXON);  // test only
@@ -9076,7 +9076,7 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p)
 	u2VrefBegin = 0;
 	u2VrefEnd = (p->dram_type==TYPE_LPDDR5?VREF_VOLTAGE_TABLE_NUM_LP5:VREF_VOLTAGE_TABLE_NUM_LP4)-1;
 	u2VrefStep = EYESCAN_GRAPH_CATX_VREF_STEP;
-	mcSHOW_DBG_MSG3(("\nTX Vref %d -> %d, step: %d\n", u2VrefBegin, u2VrefEnd, u2VrefStep));
+	msg3("\nTX Vref %d -> %d, step: %d\n", u2VrefBegin, u2VrefEnd, u2VrefStep);
 
 #if ENABLE_K_WITH_WORST_SI_UI_SHIFT
 	DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1
@@ -9090,7 +9090,7 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p)
 		//set vref
 //fra		 u1MR14Value[p->channel][p->rank][p->dram_fsp] = (u2VrefLevel | (u2VrefRange<<6));
 		DramcTXSetVref(p, u2VrefRange, u2VrefLevel);
-		mcSHOW_DBG_MSG3(("\n\n Set TX VrefRange %d, VrefLevel=%d\n", u2VrefRange, u2VrefLevel));
+		msg3("\n\n Set TX VrefRange %d, VrefLevel=%d\n", u2VrefRange, u2VrefLevel);
 
 		// initialize parameters
 		uiFinishCount = 0;
@@ -9218,7 +9218,7 @@ void Dramc_K_TX_EyeScan_Log(DRAMC_CTX_T *p)
 //fra								 gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = WinPerBit[u1BitIdx].last_pass + tx_pi_delay[u1BitIdx/8]-32;
 								gEyeScan_Min[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].first_pass;
 								gEyeScan_Max[(u2VrefLevel+u2VrefRange*30)/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]] = (S8) WinPerBit[u1BitIdx].last_pass;
-								mcSHOW_DBG_MSG3(("VrefRange %d, VrefLevel=%d, u1BitIdx=%d, index=%d (%d, %d)==\n",u2VrefRange,u2VrefLevel, u1BitIdx, EyeScan_index[u1BitIdx], gEyeScan_Min[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]], gEyeScan_Max[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]]));
+								msg3("VrefRange %d, VrefLevel=%d, u1BitIdx=%d, index=%d (%d, %d)==\n",u2VrefRange,u2VrefLevel, u1BitIdx, EyeScan_index[u1BitIdx], gEyeScan_Min[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]], gEyeScan_Max[u2VrefLevel/EYESCAN_GRAPH_CATX_VREF_STEP][u1BitIdx][EyeScan_index[u1BitIdx]]);
 								gEyeScan_MinMax_store_delay[u1BitIdx/8] =  tx_pi_delay[u1BitIdx/8]-32; /* save this information for HQA pass/fail judgement used */
 #endif
 								EyeScan_index[u1BitIdx]=EyeScan_index[u1BitIdx]+1;
@@ -9357,9 +9357,9 @@ void DramcTxOECalibration(DRAMC_CTX_T *p)
 	u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4;
 
 	#if TX_OE_PATTERN_USE_TA2
-	mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] TA2\n"));
+	msg("\n[DramC_TX_OE_Calibration] TA2\n");
 	#else
-	mcSHOW_DBG_MSG(("\n[DramC_TX_OE_Calibration] DMA\n"));
+	msg("\n[DramC_TX_OE_Calibration] DMA\n");
 	#endif
 
 	//default set FAIL
@@ -9379,9 +9379,9 @@ void DramcTxOECalibration(DRAMC_CTX_T *p)
 
 	for (u1ByteIdx = 0; u1ByteIdx < DQS_NUMBER_LP4; u1ByteIdx++)
 	{
-		mcSHOW_DBG_MSG(("Byte%d TX OE(2T, 0.5T) = (%d, %d)\n", u1ByteIdx, ucdq_oen_ui_large[u1ByteIdx], ucdq_oen_ui_small[u1ByteIdx]));
+		msg("Byte%d TX OE(2T, 0.5T) = (%d, %d)\n", u1ByteIdx, ucdq_oen_ui_large[u1ByteIdx], ucdq_oen_ui_small[u1ByteIdx]);
 	}
-	mcSHOW_DBG_MSG(("\n\n"));
+	msg("\n\n");
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_SELPH_DQ0), \
 									P_Fld(ucdq_oen_ui_large[0], SHURK_SELPH_DQ0_TXDLY_OEN_DQ0) | \
@@ -9437,7 +9437,7 @@ DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p)
 	// error handling
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context NULL\n"));
+		err("context NULL\n");
 		return DRAM_FAIL;
 	}
 
@@ -9618,7 +9618,7 @@ DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p)
 
 	for (u1RxGatingPI = u1RxGatingPI_start; u1RxGatingPI < u1RxGatingPI_end; u1RxGatingPI++)
 	{
-		mcSHOW_DBG_MSG(("\n[DramcMiockJmeter] u1RxGatingPI = %d\n", u1RxGatingPI));
+		msg("\n[DramcMiockJmeter] u1RxGatingPI = %d\n", u1RxGatingPI);
 
 		ucsearch_state = 0;
 		for (u1RankIdx = RANK_0; u1RankIdx < p->support_rank_num; u1RankIdx++)
@@ -9659,9 +9659,9 @@ DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p)
 			//u4ones_cnt[2] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT), MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT);
 			//u4ones_cnt[3] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT), MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT);
 			#ifdef ETT_PRINT_FORMAT
-			mcSHOW_DBG_MSG(("%d : %d, %d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0]));
+			msg("%d : %d, %d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0]);
 			#else
-			mcSHOW_DBG_MSG(("%3d : %8d, %8d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0]));
+			msg("%3d : %8d, %8d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0]);
 			#endif
 
 			//change to boolean value
@@ -9764,8 +9764,8 @@ DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p)
 	{
 		if (ucsearch_state != 3)
 		{
-			mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter - ch=%d\n", p->channel));
-			mcSHOW_DBG_MSG(("\tLess than 0.5T data. Cannot calculate delay cell time\n\n"));
+			msg("\n\tMIOCK jitter meter - ch=%d\n", p->channel);
+			msg("\tLess than 0.5T data. Cannot calculate delay cell time\n\n");
 
 			u2g_num_dlycell_perT = 0;	//for LP3 and LP4 lookup table used
 
@@ -9807,21 +9807,21 @@ DRAM_STATUS_T DramcMiockJmeter(DRAMC_CTX_T *p)
 
 	if (ucsearch_state == 4)
 	{ // 1T
-		mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n"
+		msg("\n\tMIOCK jitter meter\tch=%d\n\n"
 						"1T = (%d-%d) = %d dly cells\n"
 						"Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n",
 							p->channel,
 							ucend_period, ucstart_period, u2g_num_dlycell_perT,
-							u2real_freq, u2real_period, u2gdelay_cell_ps));
+							u2real_freq, u2real_period, u2gdelay_cell_ps);
 	}
 	else
 	{ // 0.5T
-		mcSHOW_DBG_MSG(("\n\tMIOCK jitter meter\tch=%d\n\n"
+		msg("\n\tMIOCK jitter meter\tch=%d\n\n"
 						"1T = (%d-%d)*2 = %d dly cells\n"
 						"Clock freq = %d MHz, period = %d ps, 1 dly cell = %d/100 ps\n",
 							p->channel,
 							ucmiddle_period, ucstart_period, u2g_num_dlycell_perT,
-							u2real_freq, u2real_period, u2gdelay_cell_ps));
+							u2real_freq, u2real_period, u2gdelay_cell_ps);
 	}
 
 	return DRAM_OK;
@@ -9973,7 +9973,7 @@ static void GetVcoreDelayCellTime(DRAMC_CTX_T *p, U8 shuffleIdx)
 		u2gdelay_cell_ps_all[shuffleIdx][channel_i] = u2gdelay_cell_ps;
 	}
 #if __ETT__
-	mcSHOW_DBG_MSG(("Freq=%d, CH_%d, VCORE=%d, cell=%d\n", p->frequency, p->channel, u4gVcore[shuffleIdx], u2gdelay_cell_ps_all[shuffleIdx][p->channel]));
+	msg("Freq=%d, CH_%d, VCORE=%d, cell=%d\n", p->frequency, p->channel, u4gVcore[shuffleIdx], u2gdelay_cell_ps_all[shuffleIdx][p->channel]);
 #endif
 
 	return;
@@ -9984,7 +9984,7 @@ void DramcMiockJmeterHQA(DRAMC_CTX_T *p)
 	//do MiockJitterMeter@DDR2667
 	U8 shuffleIdx;
 
-	mcSHOW_DBG_MSG(("[MiockJmeterHQA]\n"));
+	msg("[MiockJmeterHQA]\n");
 
 	shuffleIdx = get_shuffleIndex_by_Freq(p);
 
@@ -10008,7 +10008,7 @@ void DramcMiockJmeterHQA(DRAMC_CTX_T *p)
 	/* Use highest freq's delay cell time measurement results as reference */
 	p->u2num_dlycell_perT = u2g_num_dlycell_perT_all[shuffleIdx][p->channel];
 	p->u2DelayCellTimex100 = u2gdelay_cell_ps_all[shuffleIdx][p->channel];
-	mcSHOW_DBG_MSG3(("DelayCellTimex100 CH_%d, (VCORE=%d, cell=%d)\n",p->channel, u4gVcore[shuffleIdx], p->u2DelayCellTimex100));
+	msg3("DelayCellTimex100 CH_%d, (VCORE=%d, cell=%d)\n",p->channel, u4gVcore[shuffleIdx], p->u2DelayCellTimex100);
 }
 #endif
 
@@ -10046,13 +10046,13 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 	// error handling
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context NULL\n"));
+		err("context NULL\n");
 		return DRAM_FAIL;
 	}
 
 	if (p->frequency < 1866)
 	{
-		//mcSHOW_ERR_MSG(("skip 8-Phase Calib Freq is %d < 1866 !!!\n", p->frequency));
+		//err("skip 8-Phase Calib Freq is %d < 1866 !!!\n", p->frequency);
 		return DRAM_OK;
 	}
 
@@ -10278,13 +10278,13 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 				u18Ph_end = 32;
 				break;
 			default:
-				mcSHOW_ERR_MSG(("u18Phase_SM err!\n"));
+				err("u18Phase_SM err!\n");
 				#if __ETT__
 				while (1);
 				#endif
 		}
 
-		mcSHOW_DBG_MSG(("\n[Dramc8PhaseCal] 8-Phase SM_%d, 8PH_dly (%d~%d), DQSIEN PI = %d, 8PH_Dly = %d\n", u18Phase_SM, u18Ph_start, u18Ph_end, u1DqsienPI, u18PhDlyBackup));
+		msg("\n[Dramc8PhaseCal] 8-Phase SM_%d, 8PH_dly (%d~%d), DQSIEN PI = %d, 8PH_Dly = %d\n", u18Phase_SM, u18Ph_start, u18Ph_end, u1DqsienPI, u18PhDlyBackup);
 
 		//to see 1T(H,L) or 1T(L,H) from delaycell=0 to 127
 		//NOTE: Must set dual ranks for Rx path
@@ -10298,7 +10298,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 
 		for (u18Ph_dly = u18Ph_start; u18Ph_dly < u18Ph_end; u18Ph_dly++)
 		{
-			mcSHOW_DBG_MSG(("8PH dly = %d\n", u18Ph_dly));
+			msg("8PH dly = %d\n", u18Ph_dly);
 
 			u1DqsLevel = 0xff;
 			vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_B0_DQ1), u18Ph_dly, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0);
@@ -10331,15 +10331,15 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 				//u4ones_cnt[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS1_ERR_CNT), MISC_DUTY_DQS1_ERR_CNT_DQS1_ERR_CNT);
 				//u4ones_cnt[2] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS2_ERR_CNT), MISC_DUTY_DQS2_ERR_CNT_DQS2_ERR_CNT);
 				//u4ones_cnt[3] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_DUTY_DQS3_ERR_CNT), MISC_DUTY_DQS3_ERR_CNT_DQS3_ERR_CNT);
-				//Darren-mcSHOW_DBG_MSG(("%3d : %8d, %8d, %8d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0], u4ones_cnt[1]));
+				//Darren-msg("%3d : %8d, %8d, %8d\n", ucdqs_dly, u4sample_cnt, u4ones_cnt[0], u4ones_cnt[1]);
 
 				//change to boolean value
 				if (u4ones_cnt[0] < (u4sample_cnt / 2))
 				{
 					if (u1DqsLevel == 0xff) // print once
 					{
-						mcSHOW_DBG_MSG(("[L] %d, %8d\n", ucdqs_dly, u4ones_cnt[0]));
-						//mcSHOW_DBG_MSG(("[L] %d, %8d, %8d\n", ucdqs_dly, u4ones_cnt[0], u4ones_cnt[1]));
+						msg("[L] %d, %8d\n", ucdqs_dly, u4ones_cnt[0]);
+						//msg("[L] %d, %8d, %8d\n", ucdqs_dly, u4ones_cnt[0], u4ones_cnt[1]);
 					}
 
 					u1DqsLevel = 0;
@@ -10349,13 +10349,13 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 					if (u1DqsLevel == 0)  // from low to high
 					{
 						u1DqsLevel = 1;
-						mcSHOW_DBG_MSG(("[H] %d, %8d\n", ucdqs_dly, u4ones_cnt[0]));
-						//mcSHOW_DBG_MSG(("[H] %d, %8d, %8d\n", ucdqs_dly, u4ones_cnt[0], u4ones_cnt[1]));
+						msg("[H] %d, %8d\n", ucdqs_dly, u4ones_cnt[0]);
+						//msg("[H] %d, %8d, %8d\n", ucdqs_dly, u4ones_cnt[0], u4ones_cnt[1]);
 
 						if (u18Phase_SM == DQS_8PH_DEGREE_0)
 						{
 							u2R0 = ucdqs_dly;
-							mcSHOW_DBG_MSG(("R0 = %d\n", u2R0));
+							msg("R0 = %d\n", u2R0);
 							break; // break ucdqs_dly for loop
 						}
 						else if (u18Phase_SM == DQS_8PH_DEGREE_180)
@@ -10364,7 +10364,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 							if (u2R180 > u2R0)
 							{
 								u2R = u2R0 + ((u2R180 - u2R0) >> 2); // u2R180 >= u2R0 for (u1R180 - u1R0)/4 for 180 degree. /2 for 90 degree
-								mcSHOW_DBG_MSG(("R = %d, R180 = %d\n", u2R, u2R180));
+								msg("R = %d, R180 = %d\n", u2R, u2R180);
 								break; // break ucdqs_dly for loop
 							}
 							else
@@ -10404,7 +10404,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 									}
 								}
 
-								mcSHOW_DBG_MSG(("diff (P-R) = %d, min = %d, break count = %d\n", s2Err_code, s2Err_code_min, u1loop_cnt));
+								msg("diff (P-R) = %d, min = %d, break count = %d\n", s2Err_code, s2Err_code_min, u1loop_cnt);
 
 								break; // if (s2Err_code == s2Err_code_min) for next u18Ph_dly
 							}
@@ -10415,7 +10415,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 						}
 						else
 						{
-							mcSHOW_ERR_MSG(("u18Phase_SM err!\n"));
+							err("u18Phase_SM err!\n");
 							#if __ETT__
 							while (1);
 							#endif
@@ -10433,7 +10433,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 				// NOTE: 8-Phase calib must from 0 to 1
 				u18Ph_dly_final = u18PhDlyBackup; //rollback to init settings
 				eDRAMStatus = DRAM_FAIL;
-				mcSHOW_ERR_MSG(("\n[Dramc8PhaseCal] 8-Phase SM_%d is fail (to Default)!!!\n", u18Phase_SM));
+				err("\n[Dramc8PhaseCal] 8-Phase SM_%d is fail (to Default)!!!\n", u18Phase_SM);
 				goto exit;
 			} else if (u18Ph_dly_loop_break == 1)
 				break;
@@ -10442,7 +10442,7 @@ DRAM_STATUS_T Dramc8PhaseCal(DRAMC_CTX_T *p)
 	}
 
 exit:
-	mcSHOW_DBG_MSG(("\n[Dramc8PhaseCal] u18Ph_dly_final = %d\n\n", u18Ph_dly_final));
+	msg("\n[Dramc8PhaseCal] u18Ph_dly_final = %d\n\n", u18Ph_dly_final);
 	vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ1, u18Ph_dly_final, SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0);
 	vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ1, u18Ph_dly_final, SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1);
 	vIO32WriteFldAlign_All(DDRPHY_REG_SHU_CA_CMD1, u18Ph_dly_final, SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA);
@@ -10588,7 +10588,7 @@ static void vImpCalVrefSel(DRAMC_CTX_T *p, DRAMC_IMP_T efreq_region, U8 u1ImpCal
 	}
 	else
 	{
-		mcSHOW_ERR_MSG(("[vImpCalVrefSel] Warnning: Need confirm DRAM type for IMP_VREF_SEL !!!\n"));
+		err("[vImpCalVrefSel] Warnning: Need confirm DRAM type for IMP_VREF_SEL !!!\n");
 		#if __ETT__
 		while(1);
 		#endif
@@ -10606,13 +10606,13 @@ static void vImpCalVrefSel(DRAMC_CTX_T *p, DRAMC_IMP_T efreq_region, U8 u1ImpCal
 			u4DrvFld = SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN;
 			break;
 		default:
-			mcSHOW_ERR_MSG(("[vImpCalVrefSel] Warnning: Need confirm u1ImpCalStage for SW IMP Calibration !!!\n"));
+			err("[vImpCalVrefSel] Warnning: Need confirm u1ImpCalStage for SW IMP Calibration !!!\n");
 			break;
 	}
 
 	// dbg msg after vref_sel selection
-	mcSHOW_DBG_MSG3(("[vImpCalVrefSel] IMP_VREF_SEL 0x%x, IMPCAL stage:%u, freq_region:%u\n",
-					  u1RegTmpValue, u1ImpCalStage, efreq_region));
+	msg3("[vImpCalVrefSel] IMP_VREF_SEL 0x%x, IMPCAL stage:%u, freq_region:%u\n",
+					  u1RegTmpValue, u1ImpCalStage, efreq_region);
 
 	/* Set IMP_VREF_SEL register field's value */
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_CA_CMD12), u1RegTmpValue, u4DrvFld);
@@ -10635,11 +10635,11 @@ static U32 DramcSwImpCalResult(DRAMC_CTX_T *p, const char *drvType, U32 u4Fld)
 		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4ImpxDrv, u4Fld);
 		mcDELAY_US(1);
 		u4ImpCalResult = u4IO32ReadFldAlign((DDRPHY_REG_MISC_PHY_RGS_CMD), MISC_PHY_RGS_CMD_RGS_RIMPCALOUT);
-		mcSHOW_DBG_MSG2(("OCD %s=%d ,CALOUT=%d\n", drvType, u4ImpxDrv, u4ImpCalResult));
+		msg2("OCD %s=%d ,CALOUT=%d\n", drvType, u4ImpxDrv, u4ImpCalResult);
 
 		if (u4ImpCalResult == u4CheckImpChange)//first found
 		{
-			mcSHOW_DBG_MSG2(("\nOCD %s calibration OK! %s=%d\n\n", drvType, drvType, u4ImpxDrv));
+			msg2("\nOCD %s calibration OK! %s=%d\n\n", drvType, drvType, u4ImpxDrv);
 			break;
 		}
 	}
@@ -10647,7 +10647,7 @@ static U32 DramcSwImpCalResult(DRAMC_CTX_T *p, const char *drvType, U32 u4Fld)
 	if (u4ImpxDrv == 32) // Can't find SwImp drv results
 	{
 		u4ImpxDrv = 31;
-		mcSHOW_DBG_MSG2(("\nOCD %s calibration FAIL! %s=%d\n\n", drvType, drvType, u4ImpxDrv));
+		msg2("\nOCD %s calibration FAIL! %s=%d\n\n", drvType, drvType, u4ImpxDrv);
 	}
 
 	return u4ImpxDrv;
@@ -10735,7 +10735,7 @@ DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_re
 				u4DrvFld = SHU_MISC_IMPCAL1_IMPDRVN;
 				break;
 			default:
-				mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm u1DrvType for SW IMP Calibration !!!\n"));
+				err("[DramcSwImpedanceCal] Warnning: Need confirm u1DrvType for SW IMP Calibration !!!\n");
 				break;
 		}
 
@@ -10743,7 +10743,7 @@ DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_re
 		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENP, MISC_IMPCAL_IMPCAL_CALI_ENP);  //MISC_IMP_CTRL1_RG_IMP_OCD_PUCMP_EN move to CALI_ENP
 		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_MISC_IMPCAL), u1CALI_ENN, MISC_IMPCAL_IMPCAL_CALI_ENN);  //MISC_IMP_CTRL1_RG_RIMP_ODT_EN move to CALI_ENN
 
-		mcSHOW_DBG_MSG2(("\n\n\tK %s\n", drvStr));
+		msg2("\n\n\tK %s\n", drvStr);
 
 		//DRVP=DRVP_FINAL
 		vIO32WriteFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_MISC_IMPCAL1), u4DRVP_Result, SHU_MISC_IMPCAL1_IMPDRVP);  //PUCMP_EN move to CALI_ENP
@@ -10768,7 +10768,7 @@ DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_re
 				u4ODTN_Result = u4SwImpCalResult;
 				break;
 			default:
-				mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm u4SwImpCalResult for SW IMP Calibration !!!\n"));
+				err("[DramcSwImpedanceCal] Warnning: Need confirm u4SwImpCalResult for SW IMP Calibration !!!\n");
 				break;
 		}
 	}
@@ -10785,7 +10785,7 @@ DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_re
 	LP4X(T):  DRVP=5, DRVN=9, ODTN=14
 	LP4P: DRVP=8, DRVN=10
 ***/
-	mcSHOW_DBG_MSG(("[SwImpedanceCal] DRVP=%d, DRVN=%d, ODTN=%d\n", u4DRVP_Result, u4DRVN_Result, u4ODTN_Result));
+	msg("[SwImpedanceCal] DRVP=%d, DRVN=%d, ODTN=%d\n", u4DRVP_Result, u4DRVN_Result, u4ODTN_Result);
 
 	#if 0//HYNIX_IMPX_ADJUST
 	if (u1Para)
@@ -10817,8 +10817,8 @@ DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_re
 	}
 #endif
 
-	mcSHOW_DBG_MSG(("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP],
-									gDramcSwImpedanceResult[freq_region][DRVN], gDramcSwImpedanceResult[freq_region][ODTN]));
+	msg("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP],
+									gDramcSwImpedanceResult[freq_region][DRVN], gDramcSwImpedanceResult[freq_region][ODTN]);
 
 #if APPLY_SIGNAL_WAVEFORM_SETTINGS_ADJUST
 	if ((p->dram_type == TYPE_LPDDR4) && (freq_region == 0))
@@ -10832,24 +10832,24 @@ DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_re
 		gDramcSwImpedanceResult[freq_region][ODTN] = SwImpedanceAdjust(gDramcSwImpedanceResult[freq_region][ODTN], gDramcSwImpedanceAdjust[freq_region][ODTN]);
 	}
 
-	mcSHOW_DBG_MSG(("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d (After Adjust)\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP],
-										gDramcSwImpedanceResult[freq_region][DRVN], gDramcSwImpedanceResult[freq_region][ODTN]));
+	msg("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d (After Adjust)\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP],
+										gDramcSwImpedanceResult[freq_region][DRVN], gDramcSwImpedanceResult[freq_region][ODTN]);
 #endif
 
 #if __FLASH_TOOL_DA__
 	if((gDramcSwImpedanceResult[freq_region][ODTN] ==0)||(gDramcSwImpedanceResult[freq_region][ODTN] >=31))
 	{
-		mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, ODTN = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][ODTN]));
+		msg("[WARNING] freq_region = %d, ODTN = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][ODTN]);
 		PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+ODTN));
 	}
 	else if((gDramcSwImpedanceResult[freq_region][DRVP] ==0)||(gDramcSwImpedanceResult[freq_region][DRVP] >=31))
 	{
-		mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, DRVP = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP]));
+		msg("[WARNING] freq_region = %d, DRVP = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVP]);
 		PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+DRVP));
 	}
 	else if((gDramcSwImpedanceResult[freq_region][DRVN] ==0)||(gDramcSwImpedanceResult[freq_region][DRVN] >=31))
 	{
-		mcSHOW_DBG_MSG(("[WARNING] freq_region = %d, DRVN = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVN]));
+		msg("[WARNING] freq_region = %d, DRVN = %d ==> unexpect value\n", freq_region, gDramcSwImpedanceResult[freq_region][DRVN]);
 		PINInfo_flashtool.IMP_ERR_FLAG |= (0x1<<(freq_region+DRVN));
 	}
 	else
@@ -10857,7 +10857,7 @@ DRAM_STATUS_T DramcSwImpedanceCal(DRAMC_CTX_T *p, U8 u1Para, DRAMC_IMP_T freq_re
 	{
 	vSetCalibrationResult(p, DRAM_CALIBRATION_SW_IMPEDANCE, DRAM_OK);
 	}
-	mcSHOW_DBG_MSG3(("[DramcSwImpedanceCal] Done\n\n"));
+	msg3("[DramcSwImpedanceCal] Done\n\n");
 
 	vSetPHY2ChannelMapping(p, backup_channel);
 	DramcBroadcastOnOff(backup_broadcast);
@@ -10950,8 +10950,8 @@ static void DQSDutyScan_SetDqsDelayCell(DRAMC_CTX_T *p, S8 *scDutyDelay)
 	U32 save_offset;
 	U8 tDelay[2];
 
-//	  mcSHOW_DBG_MSG(("CH%d, Final DQS0 duty delay cell = %d\n", p->channel, scDutyDelay[0]));
-//	  mcSHOW_DBG_MSG(("CH%d, Final DQS1 duty delay cell = %d\n", p->channel, scDutyDelay[1]));
+//	  msg("CH%d, Final DQS0 duty delay cell = %d\n", p->channel, scDutyDelay[0]);
+//	  msg("CH%d, Final DQS1 duty delay cell = %d\n", p->channel, scDutyDelay[1]);
 
 	for(u1DQSIdx=0; u1DQSIdx<2; u1DQSIdx++)
 	{
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
index 11345590fa..c228c2cf9f 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_main.c
@@ -390,7 +390,7 @@ void GetVcoreDelayCellTimeFromTable(DRAMC_CTX_T *p)
 		}
 	}
 
-	mcSHOW_DBG_MSG(("[GetVcoreDelayCellTimeFromTable(%d)] VCore=%d(x100), DelayCell=%d(x100)\n", u1delay_cell_cnt, get_vcore, u2gdelay_cell_ps));
+	msg("[GetVcoreDelayCellTimeFromTable(%d)] VCore=%d(x100), DelayCell=%d(x100)\n", u1delay_cell_cnt, get_vcore, u2gdelay_cell_ps);
 
 	for(channel_i=CHANNEL_A; channel_i < p->support_channel_num; channel_i++)
 	{
@@ -429,14 +429,14 @@ void Test_Broadcast_Feature(DRAMC_CTX_T *p)
 	read_value = u4IO32Read4B(DRAMC_REG_SHURK_SELPH_DQ2 + SHIFT_TO_CHB_ADDR);
 	if (read_value != 0xA55A00FF)
 	{
-		mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n"));
+		err("Check Erro! Broad Cast CHA RG to CHB Fail!!\n");
 		while (1);
 	}
 
 	read_value = u4IO32Read4B(DDRPHY_REG_SHU_RK_B0_DQ0 + SHIFT_TO_CHB_ADDR);
 	if (read_value != 0xA55A00FF)
 	{
-		mcSHOW_ERR_MSG(("Check Erro! Broad Cast CHA RG to CHB Fail!!\n"));
+		err("Check Erro! Broad Cast CHA RG to CHB Fail!!\n");
 		while (1);
 	}
 
@@ -462,7 +462,7 @@ void Get_RX_DelayCell(DRAMC_CTX_T *p)
 		if (gHQALOG_RX_delay_cell_ps_075V == 0)
 		{
 #if __ETT__
-			mcSHOW_DBG_MSG(("RX delay cell calibration (%d):\n", hqa_vmddr_class));
+			msg("RX delay cell calibration (%d):\n", hqa_vmddr_class);
 
 			switch (hqa_vmddr_class)
 			{
@@ -518,7 +518,7 @@ void PRE_MIOCK_JMETER_HQA_USED(DRAMC_CTX_T *p)
 	backup_freq_sel = vGet_PLL_FreqSel(p);
 	backup_channel = p->channel;
 
-	mcSHOW_DBG_MSG3(("[JMETER_HQA]\n"));
+	msg3("[JMETER_HQA]\n");
 	Set_PRE_MIOCK_JMETER_HQA_USED_flag(1);
 
 	vSetPHY2ChannelMapping(p, CHANNEL_A);
@@ -548,16 +548,16 @@ static DRAM_STATUS_T DramcSave_Time_For_Cal_End(DRAMC_CTX_T *p)
 	{
 		#if EMMC_READY
 		write_offline_dram_calibration_data(p->shu_type, p->pSavetimeData);
-		mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to emmc\n"));
+		msg("[FAST_K] Save calibration result to emmc\n");
 		#else
 		g_dram_save_time_init_done[p->shu_type] = 1;
 		memcpy(&(SaveTimeDataByShuffle[p->shu_type]), p->pSavetimeData, sizeof(SAVE_TIME_FOR_CALIBRATION_T));
-		mcSHOW_DBG_MSG(("[FAST_K] Save calibration result to SW memory\n"));
+		msg("[FAST_K] Save calibration result to SW memory\n");
 		#endif
 	}
 	else
 	{
-		mcSHOW_DBG_MSG(("[FAST_K] Bypass saving calibration result to emmc\n"));
+		msg("[FAST_K] Bypass saving calibration result to emmc\n");
 	}
 
 	return DRAM_OK;
@@ -625,11 +625,11 @@ static DRAM_STATUS_T DramcSave_Time_For_Cal_Init(DRAMC_CTX_T *p)
 	}
 
 #if EMMC_READY
-	mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SHU%d, femmc_Ready=%d\n", p->shu_type, p->femmc_Ready));
+	msg("[FAST_K] DramcSave_Time_For_Cal_Init SHU%d, femmc_Ready=%d\n", p->shu_type, p->femmc_Ready);
 #else
-	mcSHOW_DBG_MSG(("[FAST_K] DramcSave_Time_For_Cal_Init SHU%d, Init_done=%d, femmc_Ready=%d\n", p->shu_type, g_dram_save_time_init_done[p->shu_type], p->femmc_Ready));
+	msg("[FAST_K] DramcSave_Time_For_Cal_Init SHU%d, Init_done=%d, femmc_Ready=%d\n", p->shu_type, g_dram_save_time_init_done[p->shu_type], p->femmc_Ready);
 #endif
-	mcSHOW_DBG_MSG(("[FAST_K] Bypass_RDDQC %d, Bypass_RXWINDOW=%d, Bypass_TXWINDOW=%d\n", p->Bypass_RDDQC, p->Bypass_RXWINDOW, p->Bypass_TXWINDOW));
+	msg("[FAST_K] Bypass_RDDQC %d, Bypass_RXWINDOW=%d, Bypass_TXWINDOW=%d\n", p->Bypass_RDDQC, p->Bypass_RXWINDOW, p->Bypass_TXWINDOW);
 
 	return DRAM_OK;
 }
@@ -655,7 +655,7 @@ static void DramRankNumberDetection(DRAMC_CTX_T *p)
 		p->support_rank_num = RANK_SINGLE;
 		vIO32WriteFldAlign(DRAMC_REG_SA_RESERVE, 1, SA_RESERVE_SINGLE_RANK);  //keep support_rank_num to reserved rg
 	}
-	mcSHOW_DBG_MSG(("[RankNumberDetection] %d\n", p->support_rank_num));
+	msg("[RankNumberDetection] %d\n", p->support_rank_num);
 
 	vSetRank(p, u1RankBak);  // restore rank setting
 }
@@ -665,7 +665,7 @@ static void UpdateGlobal10GBEnVariables(DRAMC_CTX_T *p)
 {
 	p->u110GBEn[RANK_0] = (get_row_width_by_emi(RANK_0) >= 18) ? ENABLE : DISABLE;
 	p->u110GBEn[RANK_1] = (get_row_width_by_emi(RANK_1) >= 18) ? ENABLE : DISABLE;
-	//mcSHOW_DBG_MSG(("[10GBEn] RANK0=%d, RANK1=%d\n", p->u110GBEn[RANK_0], p->u110GBEn[RANK_1]));
+	//msg("[10GBEn] RANK0=%d, RANK1=%d\n", p->u110GBEn[RANK_0], p->u110GBEn[RANK_1]);
 }
 
 void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p)
@@ -691,7 +691,7 @@ void vCalibration_Flow_For_MDL(DRAMC_CTX_T *p)
 		DramcRxWindowPerbitCal(p, PATTERN_RDDQC, NULL, AUTOK_OFF);
 
 #if MRW_CHECK_ONLY
-		mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+		mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
 		vAutoRefreshSwitch(p, DISABLE); //After gating, Rx and Tx calibration, auto refresh should be disable
 	}
@@ -719,13 +719,13 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf
 	// Read MR5 for Vendor ID
 	DramcModeRegReadByRank(p, RANK_0, 5, &(p->vendor_id));// for byte mode, don't show value of another die.
 	p->vendor_id &= 0xFF;
-	mcSHOW_DBG_MSG(("[GetDramInforAfterCalByMRR] Vendor %x.\n", p->vendor_id));
+	msg("[GetDramInforAfterCalByMRR] Vendor %x.\n", p->vendor_id);
 	// Read MR6 for Revision ID
 	DramcModeRegReadByRank(p, RANK_0, 6, &(p->revision_id));// for byte mode, don't show value of another die.
-	mcSHOW_DBG_MSG(("[GetDramInforAfterCalByMRR] Revision %x.\n", p->revision_id));
+	msg("[GetDramInforAfterCalByMRR] Revision %x.\n", p->revision_id);
 	// Read MR6 for Revision ID2
 	DramcModeRegReadByRank(p, RANK_0, 7, &u2MR7);// for byte mode, don't show value of another die.
-	mcSHOW_DBG_MSG(("[GetDramInforAfterCalByMRR] Revision 2 %x.\n", u2MR7));
+	msg("[GetDramInforAfterCalByMRR] Revision 2 %x.\n", u2MR7);
 #if (!__ETT__) && (FOR_DV_SIMULATION_USED==0)
 	set_dram_mr(5, p->vendor_id);
 	set_dram_mr(6, p->revision_id);
@@ -749,10 +749,10 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf
 		#endif
 		{
 			DramcModeRegReadByRank(p, u1RankIdx, 0, &(gu2MR0_Value[u1RankIdx]));
-			mcSHOW_DBG_MSG(("MR0 0x%x\n", gu2MR0_Value[u1RankIdx]));
+			msg("MR0 0x%x\n", gu2MR0_Value[u1RankIdx]);
 
 			DramcModeRegReadByRank(p, u1RankIdx, 8, &u2Density);
-			mcSHOW_DBG_MSG(("MR8 0x%x\n", u2Density));
+			msg("MR8 0x%x\n", u2Density);
 			u2MR8 |= (u2Density & 0xFF) << (u1RankIdx * 8);
 
 			u1DieNumber = 1;
@@ -766,31 +766,31 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf
 				///TODO: Darren, please check the value of u8Size.
 				case 0x0:
 					u8Size = 0x20000000;  //4Gb = 512MB
-					//mcSHOW_DBG_MSG(("[EMI]DRAM density = 4Gb\n"));
+					//msg("[EMI]DRAM density = 4Gb\n");
 					break;
 				case 0x1:
 					u8Size = 0x30000000;  //6Gb = 768MB
-					//mcSHOW_DBG_MSG(("[EMI]DRAM density = 6Gb\n"));
+					//msg("[EMI]DRAM density = 6Gb\n");
 					break;
 				case 0x2:
 					u8Size = 0x40000000;  //8Gb = 1GB = 2^30 bytes = 0x40000000 bytes
-					//mcSHOW_DBG_MSG(("[EMI]DRAM density = 8Gb\n"));
+					//msg("[EMI]DRAM density = 8Gb\n");
 					break;
 				case 0x3:
 					u8Size = 0x60000000;  //12Gb = 1.5GB = 3^30 bytes = 0x60000000 bytes
-					//mcSHOW_DBG_MSG(("[EMI]DRAM density = 12Gb\n"));
+					//msg("[EMI]DRAM density = 12Gb\n");
 					break;
 				case 0x4:
 					u8Size = 0x80000000;  //16Gb = 2GB = 4^30 bytes = 0x80000000 bytes
-					//mcSHOW_DBG_MSG(("[EMI]DRAM density = 16Gb\n"));
+					//msg("[EMI]DRAM density = 16Gb\n");
 					break;
 				case 0x5:
 					u8Size = 0xc0000000; //24Gb = 3GB = 6^30 bytes = 0xc0000000 bytes
-					//mcSHOW_DBG_MSG(("[EMI]DRAM density = 24Gb\n"));
+					//msg("[EMI]DRAM density = 24Gb\n");
 					break;
 				case 0x6:
 					u8Size = 0x100000000L; //32Gb = 4GB = 8^30 bytes = 0x10000000 bytes
-					//mcSHOW_DBG_MSG(("[EMI]DRAM density = 32Gb\n"));
+					//msg("[EMI]DRAM density = 32Gb\n");
 					break;
 				default:
 					u8Size = 0; //reserved
@@ -811,7 +811,7 @@ static int GetDramInforAfterCalByMRR(DRAMC_CTX_T *p, DRAM_INFO_BY_MRR_T *DramInf
 		}
 		// 1GB = 2^30 bytes
 		// u8Size * (2^3) / (2^30)	==>Gb
-		mcSHOW_DBG_MSG(("RK%d, DieNum %d, Density %dGb, RKsize %dGb.\n\n", u1RankIdx, u1DieNumber, (U32)(u8Size >> 27), (U32)(p->ranksize[u1RankIdx] >> 27)));
+		msg("RK%d, DieNum %d, Density %dGb, RKsize %dGb.\n\n", u1RankIdx, u1DieNumber, (U32)(u8Size >> 27), (U32)(p->ranksize[u1RankIdx] >> 27));
 	}
 #if (!__ETT__) && (FOR_DV_SIMULATION_USED==0)
 	set_dram_mr(8, u2MR8);
@@ -838,7 +838,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 
 #ifdef DDR_INIT_TIME_PROFILING
 	CPU_Cycle=TimeProfileEnd();
-	mcSHOW_TIME_MSG(("\tRX input cal takes %d us\n", CPU_Cycle));
+	time_msg("\tRX input cal takes %d us\n", CPU_Cycle);
 	TimeProfileBegin();
 #endif
 #endif
@@ -873,7 +873,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 
 		#ifdef DDR_INIT_TIME_PROFILING
 		CPU_Cycle=TimeProfileEnd();
-		mcSHOW_TIME_MSG(("\tRank %d CBT takes %d us\n", s1RankIdx, CPU_Cycle));
+		time_msg("\tRank %d CBT takes %d us\n", s1RankIdx, CPU_Cycle);
 		TimeProfileBegin();
 		#endif
 	}
@@ -900,17 +900,17 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 		{
 			if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) // skip for DDR800 rank1
 			{
-				mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n"));
+				msg("\n----->DramcWriteLeveling(PI) begin...\n");
 
 				DramcWriteLeveling(p, AUTOK_OFF, PI_BASED);
 
-				mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n"));
+				msg("DramcWriteLeveling(PI) end<-----\n\n");
 			}
 		}
 
 		#ifdef DDR_INIT_TIME_PROFILING
 		CPU_Cycle=TimeProfileEnd();
-		mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle));
+		time_msg("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle);
 		TimeProfileBegin();
 		#endif
 	}
@@ -938,15 +938,15 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 		{
 			if (!(u1IsLP4Div4DDR800(p) && (p->rank == RANK_1))) // skip for DDR800 rank1
 			{
-				mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n"));
+				msg("\n----->DramcWriteLeveling(PI) begin...\n");
 
 				DramcWriteLeveling(p, AUTOK_ON, PI_BASED);
 
-				mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n"));
+				msg("DramcWriteLeveling(PI) end<-----\n\n");
 			}
 			#ifdef DDR_INIT_TIME_PROFILING
 			CPU_Cycle=TimeProfileEnd();
-			mcSHOW_TIME_MSG(("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle));
+			time_msg("\tRank %d Write leveling takes %d us\n", s1RankIdx, CPU_Cycle);
 			TimeProfileBegin();
 			#endif
 		}
@@ -958,7 +958,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 
 		#ifdef DDR_INIT_TIME_PROFILING
 		CPU_Cycle=TimeProfileEnd();
-		mcSHOW_TIME_MSG(("\tRank %d Gating takes %d us\n", s1RankIdx, CPU_Cycle));
+		time_msg("\tRank %d Gating takes %d us\n", s1RankIdx, CPU_Cycle);
 		TimeProfileBegin();
 		#endif
 
@@ -966,12 +966,12 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 
 		#ifdef DDR_INIT_TIME_PROFILING
 		CPU_Cycle=TimeProfileEnd();
-		mcSHOW_TIME_MSG(("\tRank %d RX RDDQC takes %d us\n", s1RankIdx, CPU_Cycle));
+		time_msg("\tRank %d RX RDDQC takes %d us\n", s1RankIdx, CPU_Cycle);
 		TimeProfileBegin();
 		#endif
 
 #if MRW_CHECK_ONLY
-		mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+		mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
 
 		DramcTxWindowPerbitCal(p, TX_DQ_DQS_MOVE_DQ_DQM, FALSE, AUTOK_OFF);
@@ -990,7 +990,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 		if ((p->DBI_W_onoff[p->dram_fsp]==DBI_ON))
 		{
 			// K DQM with DBI_ON, and check DQM window spec.
-			//mcSHOW_DBG_MSG(("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n"));
+			//msg("[TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.\n\n");
 			vSwitchWriteDBISettings(p, DBI_ON);
 			DramcTxWindowPerbitCal((DRAMC_CTX_T *) p, TX_DQ_DQS_MOVE_DQM_ONLY, FALSE, AUTOK_OFF);
 			vSwitchWriteDBISettings(p, DBI_OFF);
@@ -1004,7 +1004,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 
 		#ifdef DDR_INIT_TIME_PROFILING
 		CPU_Cycle=TimeProfileEnd();
-		mcSHOW_TIME_MSG(("\tRank %d TX calibration takes %d us\n", s1RankIdx, CPU_Cycle));
+		time_msg("\tRank %d TX calibration takes %d us\n", s1RankIdx, CPU_Cycle);
 		TimeProfileBegin();
 		#endif
 
@@ -1012,7 +1012,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 
 		#ifdef DDR_INIT_TIME_PROFILING
 		CPU_Cycle=TimeProfileEnd();
-		mcSHOW_TIME_MSG(("\tRank %d Datlat takes %d us\n", s1RankIdx, CPU_Cycle));
+		time_msg("\tRank %d Datlat takes %d us\n", s1RankIdx, CPU_Cycle);
 		TimeProfileBegin();
 		#endif
 
@@ -1023,7 +1023,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 
 		#ifdef DDR_INIT_TIME_PROFILING
 		CPU_Cycle=TimeProfileEnd();
-		mcSHOW_TIME_MSG(("\tRank %d RX calibration takes %d us\n", s1RankIdx, CPU_Cycle));
+		time_msg("\tRank %d RX calibration takes %d us\n", s1RankIdx, CPU_Cycle);
 		TimeProfileBegin();
 		#endif
 	   // DramcRxdqsGatingCal(p);
@@ -1064,7 +1064,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 			for(u1ByteIdx =0 ; u1ByteIdx<(p->data_width/DQS_BIT_NUMBER); u1ByteIdx++)
 			{
 				u1HighFreqRXVref[u1ByteIdx] = (gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx] + gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx]) >> 1;
-				mcSHOW_DBG_MSG(("RX Vref Byte%d (u1HighFreqRXVref) = %d = (%d+ %d)>>1\n", u1ByteIdx, u1HighFreqRXVref[u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx]));
+				msg("RX Vref Byte%d (u1HighFreqRXVref) = %d = (%d+ %d)>>1\n", u1ByteIdx, u1HighFreqRXVref[u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_0][u1ByteIdx], gFinalRXVrefDQ[p->channel][RANK_1][u1ByteIdx]);
 			}
 
 			for(s1RankIdx=RANK_0; s1RankIdx < u1RankMax; s1RankIdx++)
@@ -1117,7 +1117,7 @@ static void vCalibration_Flow_LP4(DRAMC_CTX_T *p)
 
 	#ifdef DDR_INIT_TIME_PROFILING
 	CPU_Cycle=TimeProfileEnd();
-	mcSHOW_TIME_MSG(("\tMisc takes %d us\n\n", s1RankIdx, CPU_Cycle));
+	time_msg("\tMisc takes %d us\n\n", s1RankIdx, CPU_Cycle);
 	#endif
 }
 
@@ -1171,7 +1171,7 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p)
 	#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
 	if (p->femmc_Ready == 1)
 	{
-		mcSHOW_DBG_MSG(("\nCalibration fast K is enable, cannot show HQA measurement information\n"));
+		msg("\nCalibration fast K is enable, cannot show HQA measurement information\n");
 	}
 	else
 	#endif
@@ -1259,9 +1259,9 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p)
 	}
 
 	vSetPHY2ChannelMapping(p, backup_channel);
-	mcSHOW_DBG_MSG(("TX_TRACKING: ON\n"));
+	msg("TX_TRACKING: ON\n");
 #else
-	mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n"));
+	msg("TX_TRACKING: OFF\n");
 #endif
 
 
@@ -1272,10 +1272,10 @@ void vDramCalibrationAllChannel(DRAMC_CTX_T *p)
 #ifdef DDR_INIT_TIME_PROFILING
 #if __ETT__
 	u4low_tick1 = GPT_GetTickCount(&u4high_tick1);
-	mcSHOW_TIME_MSG(("	(4) vDramCalibrationAllChannel() take %d ms\n\r", ((u4low_tick1 - u4low_tick0) * 76) / 1000000));
+	time_msg("	(4) vDramCalibrationAllChannel() take %d ms\n\r", ((u4low_tick1 - u4low_tick0) * 76) / 1000000);
 #else
 	u4low_tick1 = get_timer(u4low_tick0);
-	mcSHOW_TIME_MSG(("	(4) vDramCalibrationAllChannel() take %d ms\n\r", u4low_tick1));
+	time_msg("	(4) vDramCalibrationAllChannel() take %d ms\n\r", u4low_tick1);
 #endif
 #endif
 }
@@ -1350,12 +1350,12 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e
 			p->dram_cbt_mode[RANK_1] = CBT_NORMAL_MODE;
 			break;
 		default:
-			mcSHOW_ERR_MSG(("Error!"));
+			err("Error!");
 			break;
 	}
-	mcSHOW_DBG_MSG2(("dram_cbt_mode_extern: %d\n"
+	msg2("dram_cbt_mode_extern: %d\n"
 					  "dram_cbt_mode [RK0]: %d, [RK1]: %d\n",
-					  (int)dram_cbt_mode_extern, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1]));
+					  (int)dram_cbt_mode_extern, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1]);
 
 #if ENABLE_APB_MASK_WRITE
 	U32 u4GPTTickCnt;
@@ -1365,7 +1365,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e
 	DramcRegAPBWriteMask(p);
 
 	u4GPTTickCnt = TimeProfileEnd();
-	mcSHOW_TIME_MSG(("[DramcRegAPBWriteMask] take %d ms\n", u4GPTTickCnt / 1000));
+	time_msg("[DramcRegAPBWriteMask] take %d ms\n", u4GPTTickCnt / 1000);
 
 	TestAPBMaskWriteFunc(p);
 
@@ -1397,7 +1397,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e
 	}
 #endif
 
-	mcSHOW_DBG_MSG(("\n\n[Bian_co] ETT version 0.0.0.1\n dram_type %d, R0 cbt_mode %d, R1 cbt_mode %d VENDOR=%d\n\n", p->dram_type, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1], p->vendor_id));
+	info("\n\n[Bian_co] ETT version 0.0.0.1\n dram_type %d, R0 cbt_mode %d, R1 cbt_mode %d VENDOR=%d\n\n", p->dram_type, p->dram_cbt_mode[RANK_0], p->dram_cbt_mode[RANK_1], p->vendor_id);
 
 #if __Petrus_TO_BE_PORTING__
 	vDramcInit_PreSettings(p);
@@ -1435,7 +1435,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e
 	}
 	else
 	{
-		mcSHOW_ERR_MSG(("[DramcSwImpedanceCal] Warnning: Need confirm DRAM type for SW IMP Calibration !!!\n"));
+		err("[DramcSwImpedanceCal] Warnning: Need confirm DRAM type for SW IMP Calibration !!!\n");
 		#if __ETT__
 		while (1);
 		#endif
@@ -1444,12 +1444,12 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e
 
 #ifdef DDR_INIT_TIME_PROFILING
 	CPU_Cycle = TimeProfileEnd();
-	mcSHOW_TIME_MSG(("(0)Pre_Init + SwImdepance takes %d ms\n\r", CPU_Cycle / 1000));
+	time_msg("(0)Pre_Init + SwImdepance takes %d ms\n\r", CPU_Cycle / 1000);
 #endif
 
 #ifdef DUMP_INIT_RG_LOG_TO_DE
 	gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag = 1;
-	mcSHOW_DUMP_INIT_RG_MSG(("\n\n//=== DDR\033[1;32m%d\033[m\n",p->frequency<<1));
+	mcSHOW_DUMP_INIT_RG_MSG("\n\n//=== DDR\033[1;32m%d\033[m\n",p->frequency<<1);
 #endif
 
 	//Clk free run
@@ -1595,7 +1595,7 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e
 	U32 u4err_value;
 	DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_PREPARE_DATA_ONLY, p->support_channel_num);
 	u4err_value = DramcDmaEngine((DRAMC_CTX_T *)p, 0x50000000, 0x60000000, 0xff00, 8, DMA_CHECK_DATA_ACCESS_AND_COMPARE, p->support_channel_num);
-	mcSHOW_DBG_MSG(("DramC_TX_OE_Calibration  0x%X\n", u4err_value));
+	msg("DramC_TX_OE_Calibration  0x%X\n", u4err_value);
 #endif
 
 #if !LCPLL_IC_SCAN
@@ -1626,12 +1626,12 @@ int Init_DRAM(DRAM_DRAM_TYPE_T dram_type, DRAM_CBT_MODE_EXTERN_T dram_cbt_mode_e
 	vGetErrorTypeResult(p);
 	#endif
 	#if CPU_RW_TEST_AFTER_K
-	mcSHOW_DBG_MSG(("\n[MEM_TEST] 02: After DFS, before run time config\n"));
+	msg("\n[MEM_TEST] 02: After DFS, before run time config\n");
 	vDramCPUReadWriteTestAfterCalibration(p);
 #endif
 
 	#if TA2_RW_TEST_AFTER_K
-	mcSHOW_DBG_MSG(("\n[TA2_TEST]\n"));
+	msg("\n[TA2_TEST]\n");
 	TA2_Test_Run_Time_HW(p);
 	#endif
 
@@ -1644,7 +1644,7 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l
 #endif
 	{
 		EnableDFSHwModeClk(p);
-		mcSHOW_DBG_MSG(("DFS_SHUFFLE_HW_MODE: ON\n"));
+		msg("DFS_SHUFFLE_HW_MODE: ON\n");
 		if (gAndroid_DVFS_en == TRUE) // shuffle to DDR3733 boot
 		{
 #if defined(SLT)
@@ -1667,20 +1667,20 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l
 
 		EnableDramcTrackingBySPMControl(p);
 
-		mcSHOW_DBG_MSG(("\n\nSettings after calibration\n\n"));
-		mcDUMP_REG_MSG(("\n\nSettings after calibration\n\n"));
+		msg("\n\nSettings after calibration\n\n");
+		reg_msg("\n\nSettings after calibration\n\n");
 #endif
 
 		DramcRunTimeConfig(p);
 	}
 
 	#if CPU_RW_TEST_AFTER_K
-	mcSHOW_DBG_MSG(("\n[MEM_TEST] 03: After run time config\n"));
+	msg("\n[MEM_TEST] 03: After run time config\n");
 	vDramCPUReadWriteTestAfterCalibration(p);
 	#endif
 
 	#if TA2_RW_TEST_AFTER_K
-	mcSHOW_DBG_MSG(("\n[TA2_TEST]\n"));
+	msg("\n[TA2_TEST]\n");
 	TA2_Test_Run_Time_HW(p);
 	#endif
 
@@ -1692,13 +1692,13 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l
 		//if ((s4value = dramc_complex_mem_test (0x46000000, 0x2000)) == 0)
 		if ((s4value = dramc_complex_mem_test (0x40024000, 0x20000)) == 0)
 		{
-			mcSHOW_DBG_MSG(("1st complex R/W mem test pass\n"));
+			msg("1st complex R/W mem test pass\n");
 		}
 		else
 		{
-			mcSHOW_DBG_MSG(("1st complex R/W mem test fail :-%d\n", -s4value));
+			msg("1st complex R/W mem test fail :-%d\n", -s4value);
 #if defined(SLT)
-			mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000\n"));
+			err("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000\n");
 			while (1);
 #endif
 		}
@@ -1711,7 +1711,7 @@ if (u2TimeProfileCnt == (DDR_INIT_TIME_PROFILING_TEST_CNT - 1)) //last time of l
 
 #ifdef DDR_INIT_TIME_PROFILING
 	CPU_Cycle = TimeProfileEnd();
-	mcSHOW_TIME_MSG(("	(5) After calibration takes %d ms\n\r", CPU_Cycle / 1000));
+	time_msg("	(5) After calibration takes %d ms\n\r", CPU_Cycle / 1000);
 #endif	// end of DDR_INIT_TIME_PROFILING
 
 #endif//SW_CHANGE_FOR_SIMULATION
@@ -1745,7 +1745,7 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 		vSetRank(DramConfig, ii);
 
 		if (!psra || psra->cbt) {
-			mcSHOW_DBG_MSG(("\n----->DramcCBT begin...\n"));
+			msg("\n----->DramcCBT begin...\n");
 			timestamp_show();
 		#if CBT_O1_PINMUX_WORKAROUND
 			CmdBusTrainingLP45(DramConfig, AUTOK_OFF); //Cannot use aito-k in A60868
@@ -1756,12 +1756,12 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 				CmdBusTrainingLP45(DramConfig, AUTOK_OFF);
 		#endif
 			timestamp_show();
-			mcSHOW_DBG_MSG(("DramcCBT end<-----\n\n"));
+			msg("DramcCBT end<-----\n\n");
 		}
 	#if ENABLE_EYESCAN_GRAPH
-	   mcSHOW_DBG_MSG(("CBT EYESCAN start<-----\n\n"));
+	   msg("CBT EYESCAN start<-----\n\n");
 	   print_EYESCAN_LOG_message(DramConfig, 0); //draw CBT eyescan
-	   mcSHOW_DBG_MSG(("CBT EYESCAN end<-----\n\n"));
+	   msg("CBT EYESCAN end<-----\n\n");
 	   #endif
 	}
 
@@ -1788,7 +1788,7 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 		if (!(u1IsLP4Div4DDR800(DramConfig) && (DramConfig->rank == RANK_1))) // skip for DDR800 rank1
 		{
 			if (!psra || psra->wl) {
-				mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(PI) begin...\n"));
+				msg("\n----->DramcWriteLeveling(PI) begin...\n");
 				timestamp_show();
 				if (psra)
 				{
@@ -1798,7 +1798,7 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 					DramcWriteLeveling(DramConfig, AUTOK_OFF, PI_BASED);
 
 				timestamp_show();
-				mcSHOW_DBG_MSG(("DramcWriteLeveling(PI) end<-----\n\n"));
+				msg("DramcWriteLeveling(PI) end<-----\n\n");
 			}
 		}
 	}
@@ -1808,20 +1808,20 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 
 #if 1//(SIMULATION_GATING == 1)
 		if (!psra || psra->gating) {
-			mcSHOW_DBG_MSG(("\n----->DramcGating begin...\n"));
+			msg("\n----->DramcGating begin...\n");
 			timestamp_show();
 			if (psra)
 				dramc_rx_dqs_gating_cal(DramConfig, psra->gating_autok, 0);
 			else
 				dramc_rx_dqs_gating_cal(DramConfig, AUTOK_OFF, 0);
 			timestamp_show();
-			mcSHOW_DBG_MSG(("DramcGating end < -----\n\n"));
+			msg("DramcGating end < -----\n\n");
 		}
 #endif
 
 #if 1//(SIMULATION_RX_RDDQC == 1)
 		if (!psra || psra->rddqc) {
-			mcSHOW_DBG_MSG(("\n----->DramcRxWindowPerbitCal RDDQC begin...\n"));
+			msg("\n----->DramcRxWindowPerbitCal RDDQC begin...\n");
 			timestamp_show();
 
 			#if 0 // Used when testing LP5 RK1 WCK2CK in high efficiency mode and differential mode.
@@ -1835,7 +1835,7 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 			#endif
 			DramcRxWindowPerbitCal(DramConfig, PATTERN_RDDQC, NULL, AUTOK_OFF);
 			timestamp_show();
-			mcSHOW_DBG_MSG(("DramcRxWindowPerbitCal end<-----\n\n"));
+			msg("DramcRxWindowPerbitCal end<-----\n\n");
 		}
 #endif // (SIMULATION_RX_RDDQC == 1)
 
@@ -1844,17 +1844,17 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 		if (is_lp5_family(DramConfig) && DramConfig->frequency >= GetFreqBySel(DramConfig,LP5_DDR4266))
 		{
 			if (!psra) {
-				mcSHOW_DBG_MSG(("\n----->DramcDutyCycleMonitor begin...\n"));
+				msg("\n----->DramcDutyCycleMonitor begin...\n");
 				timestamp_show();
 				DramcDutyCycleMonitor(DramConfig);
 				timestamp_show();
-				mcSHOW_DBG_MSG(("DramcDutyCycleMonitor end<-----\n\n"));
+				msg("DramcDutyCycleMonitor end<-----\n\n");
 
-				mcSHOW_DBG_MSG(("\n----->DramcWriteLeveling(DLY) begin...\n"));
+				msg("\n----->DramcWriteLeveling(DLY) begin...\n");
 				timestamp_show();
 				DramcWriteLeveling(DramConfig, psra->wl_autok, DLY_BASED);
 				timestamp_show();
-				mcSHOW_DBG_MSG(("DramcWriteLeveling(DLY)end<-----\n\n"));
+				msg("DramcWriteLeveling(DLY)end<-----\n\n");
 			}
 		}
 #endif /* (SIMULATION_DUTY_CYC_MONITOR == 1) */
@@ -1862,7 +1862,7 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 
 #if 1//(SIMULATION_TX_PERBIT == 1)
 		if (!psra || psra->tx_perbit) {
-			mcSHOW_DBG_MSG(("\n----->DramcTxWindowPerbitCal begin...\n"));
+			msg("\n----->DramcTxWindowPerbitCal begin...\n");
 			timestamp_show();
 			if (psra)
 				DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_DQM,
@@ -1885,32 +1885,32 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 				DramcTxWindowPerbitCal(DramConfig, TX_DQ_DQS_MOVE_DQ_ONLY,
 						FALSE, AUTOK_OFF);
 			timestamp_show();
-			mcSHOW_DBG_MSG(("DramcTxWindowPerbitCal end<-----\n\n"));
+			msg("DramcTxWindowPerbitCal end<-----\n\n");
 
 		#if ENABLE_EYESCAN_GRAPH
-			   mcSHOW_DBG_MSG(("\n----->DramcTxEYESCAN begin...\n"));
+			   msg("\n----->DramcTxEYESCAN begin...\n");
 			   Dramc_K_TX_EyeScan_Log(DramConfig);
 			   print_EYESCAN_LOG_message(DramConfig, 2); //draw TX eyescan
-			   mcSHOW_DBG_MSG(("\n----->DramcTxEYESCAN end...\n"));
+			   msg("\n----->DramcTxEYESCAN end...\n");
 			   #endif
 		}
 #endif // (SIMULATION_TX_PERBIT == 1)
 
 #if 1//(SIMULATION_DATLAT == 1)
 		if (1) { // No parameter in correspondence with by now
-			mcSHOW_DBG_MSG(("\n----->DramcRxdatlatCal begin...\n"));
+			msg("\n----->DramcRxdatlatCal begin...\n");
 			timestamp_show();
 
 			DramcRxdatlatCal(DramConfig);
 
 			timestamp_show();
-			mcSHOW_DBG_MSG(("DramcRxdatlatCal end<-----\n\n"));
+			msg("DramcRxdatlatCal end<-----\n\n");
 		}
 #endif // (SIMULATION_DATLAT == 1)
 
 #if 1//(SIMULATION_RX_PERBIT == 1)
 		if (!psra || psra->rx_perbit) {
-			mcSHOW_DBG_MSG(("\n----->DramcRxWindowPerbitCal begin...\n"));
+			msg("\n----->DramcRxWindowPerbitCal begin...\n");
 			timestamp_show();
 			if (psra)
 				DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE,
@@ -1919,12 +1919,12 @@ static void DPI_vDramCalibrationSingleChannel(DRAMC_CTX_T *DramConfig, cal_sv_ra
 				DramcRxWindowPerbitCal(DramConfig, PATTERN_TEST_ENGINE,
 						NULL /*Set Vref = 0 to test*/, AUTOK_OFF);
 			timestamp_show();
-			mcSHOW_DBG_MSG(("DramcRxWindowPerbitCal end<-----\n\n"));
+			msg("DramcRxWindowPerbitCal end<-----\n\n");
 
 			#if ENABLE_EYESCAN_GRAPH
-			   mcSHOW_DBG_MSG(("DramcRxWindowPerbitCal EYESCAN start<-----\n\n"));
+			   msg("DramcRxWindowPerbitCal EYESCAN start<-----\n\n");
 			   print_EYESCAN_LOG_message(DramConfig, 1); //draw RX eyescan
-			   mcSHOW_DBG_MSG(("DramcRxWindowPerbitCal EYESCAN end<-----\n\n"));
+			   msg("DramcRxWindowPerbitCal EYESCAN end<-----\n\n");
 			#endif
 		}
 #endif // (SIMULATION_RX_PERBIT == 1)
@@ -2076,9 +2076,9 @@ static void DPI_vDramCalibrationAllChannel(DRAMC_CTX_T *DramConfig, cal_sv_rand_
 	}
 
 	vSetPHY2ChannelMapping(DramConfig, backup_channel);
-	mcSHOW_DBG_MSG(("TX_TRACKING: ON\n"));
+	msg("TX_TRACKING: ON\n");
 #else
-	mcSHOW_DBG_MSG(("TX_TRACKING: OFF\n"));
+	msg("TX_TRACKING: OFF\n");
 #endif
 
 ///TODO: wait for porting ---
@@ -2103,29 +2103,29 @@ void EnablePLLtoSPMControl(DRAMC_CTX_T *p)
 
 void dump_dramc_ctx(DRAMC_CTX_T *p)
 {
-	mcSHOW_DBG_MSG(("== DRAMC_CTX_T ==\n"));
-	mcSHOW_DBG_MSG(("support_channel_num:	 %d\n", p->support_channel_num));
-	mcSHOW_DBG_MSG(("channel:				 %d\n", p->channel));
-	mcSHOW_DBG_MSG(("support_rank_num:		 %d\n", p->support_rank_num));
-	mcSHOW_DBG_MSG(("rank:					 %d\n", p->rank));
-	mcSHOW_DBG_MSG(("freq_sel:				 %d\n", p->freq_sel));
-	mcSHOW_DBG_MSG(("shu_type:				 %d\n", p->shu_type));
-	mcSHOW_DBG_MSG(("dram_type: 			 %d\n", p->dram_type));
-	mcSHOW_DBG_MSG(("dram_fsp:				 %d\n", p->dram_fsp));
-	mcSHOW_DBG_MSG(("odt_onoff: 			 %d\n", p->odt_onoff));
-	mcSHOW_DBG_MSG(("dram_cbt_mode: 		 %d, %d\n", (int)p->dram_cbt_mode[0], (int)p->dram_cbt_mode[1]));
-	mcSHOW_DBG_MSG(("DBI_R_onoff:			 %d, %d\n", (int)p->DBI_R_onoff[0], (int)p->DBI_R_onoff[1]));
-	mcSHOW_DBG_MSG(("DBI_W_onoff:			 %d, %d\n", (int)p->DBI_W_onoff[0], (int)p->DBI_W_onoff[1]));
-	mcSHOW_DBG_MSG(("data_width:			 %d\n", p->data_width));
-	mcSHOW_DBG_MSG(("test2_1:			  0x%x\n", p->test2_1));
-	mcSHOW_DBG_MSG(("test2_2:			  0x%x\n", p->test2_2));
-	mcSHOW_DBG_MSG(("frequency: 			 %d\n", p->frequency));
-	mcSHOW_DBG_MSG(("freqGroup: 			 %d\n", p->freqGroup));
-	mcSHOW_DBG_MSG(("lp5_training_mode: 			 %d\n", p->lp5_training_mode));
-	mcSHOW_DBG_MSG(("lp5_cbt_phase: 			 %d\n", p->lp5_cbt_phase));
-	mcSHOW_DBG_MSG(("new_cbt_mode:				%d\n", p->new_cbt_mode));
-	mcSHOW_DBG_MSG(("u1PLLMode: 			 %d\n", p->u1PLLMode));
-	mcSHOW_DBG_MSG(("curDBIState:			   %d\n", p->curDBIState));
+	msg("== DRAMC_CTX_T ==\n");
+	msg("support_channel_num:	 %d\n", p->support_channel_num);
+	msg("channel:				 %d\n", p->channel);
+	msg("support_rank_num:		 %d\n", p->support_rank_num);
+	msg("rank:					 %d\n", p->rank);
+	msg("freq_sel:				 %d\n", p->freq_sel);
+	msg("shu_type:				 %d\n", p->shu_type);
+	msg("dram_type: 			 %d\n", p->dram_type);
+	msg("dram_fsp:				 %d\n", p->dram_fsp);
+	msg("odt_onoff: 			 %d\n", p->odt_onoff);
+	msg("dram_cbt_mode: 		 %d, %d\n", (int)p->dram_cbt_mode[0], (int)p->dram_cbt_mode[1]);
+	msg("DBI_R_onoff:			 %d, %d\n", (int)p->DBI_R_onoff[0], (int)p->DBI_R_onoff[1]);
+	msg("DBI_W_onoff:			 %d, %d\n", (int)p->DBI_W_onoff[0], (int)p->DBI_W_onoff[1]);
+	msg("data_width:			 %d\n", p->data_width);
+	msg("test2_1:			  0x%x\n", p->test2_1);
+	msg("test2_2:			  0x%x\n", p->test2_2);
+	msg("frequency: 			 %d\n", p->frequency);
+	msg("freqGroup: 			 %d\n", p->freqGroup);
+	msg("lp5_training_mode: 			 %d\n", p->lp5_training_mode);
+	msg("lp5_cbt_phase: 			 %d\n", p->lp5_cbt_phase);
+	msg("new_cbt_mode:				%d\n", p->new_cbt_mode);
+	msg("u1PLLMode: 			 %d\n", p->u1PLLMode);
+	msg("curDBIState:			   %d\n", p->curDBIState);
 }
 
 
@@ -2192,7 +2192,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
 		/*
 		 * for SA's simulation
 		 */
-		mcSHOW_DBG_MSG(("enter SA's simulation flow.\n"));
+		msg("enter SA's simulation flow.\n");
 		p->support_channel_num = CHANNEL_SINGLE;
 		p->channel = CHANNEL_A;
 		p->support_rank_num = RANK_DUAL;
@@ -2275,7 +2275,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
 		/*
 		 * for DV's regression
 		 */
-		mcSHOW_DBG_MSG(("enter DV's regression flow.\n"));
+		msg("enter DV's regression flow.\n");
 		p->support_channel_num = CHANNEL_SINGLE;
 		p->channel = psra->calibration_channel;
 		p->support_rank_num = RANK_DUAL;
@@ -2342,44 +2342,44 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
 	#define __FW_VER__ "All struct move done, new RX range -- 444"
 
 	if (u1IsLP4Family(p->dram_type)) {
-		mcSHOW_DBG_MSG(("%s enter == LP4 == ...%s\n", __FUNCTION__, __FW_VER__));
+		msg("%s enter == LP4 == ...%s\n", __FUNCTION__, __FW_VER__);
 	} else {
-		mcSHOW_DBG_MSG(("%s enter == LP5 == ...%s\n", __FUNCTION__, __FW_VER__));
+		msg("%s enter == LP5 == ...%s\n", __FUNCTION__, __FW_VER__);
 	}
-	mcSHOW_DBG_MSG((CHK_INCLUDE_LOCAL_HEADER));
-
-	mcSHOW_DBG_MSG(("SIMULATION_LP4_ZQ			 ... %d\n", SIMULATION_LP4_ZQ));
-	mcSHOW_DBG_MSG(("SIMULATION_SW_IMPED		 ... %d\n", SIMULATION_SW_IMPED));
-	mcSHOW_DBG_MSG(("SIMULATION_MIOCK_JMETER	 ... %d\n", SIMULATION_MIOCK_JMETER));
-	mcSHOW_DBG_MSG(("SIMULATION_8PHASE			 ... %d\n", SIMULATION_8PHASE));
-	mcSHOW_DBG_MSG(("SIMULATION_RX_INPUT_BUF	 ... %d\n", SIMULATION_RX_INPUT_BUF));
-	mcSHOW_DBG_MSG(("SIMUILATION_CBT			 ... %d\n", SIMUILATION_CBT));
-	mcSHOW_DBG_MSG(("SIMULATION_WRITE_LEVELING	 ... %d\n", SIMULATION_WRITE_LEVELING));
-	mcSHOW_DBG_MSG(("SIMULATION_DUTY_CYC_MONITOR ... %d\n", SIMULATION_DUTY_CYC_MONITOR));
-	mcSHOW_DBG_MSG(("SIMULATION_GATING			 ... %d\n", SIMULATION_GATING));
-	mcSHOW_DBG_MSG(("SIMULATION_DATLAT			 ... %d\n", SIMULATION_DATLAT));
-	mcSHOW_DBG_MSG(("SIMULATION_RX_RDDQC		 ... %d\n", SIMULATION_RX_RDDQC));
-	mcSHOW_DBG_MSG(("SIMULATION_RX_PERBIT		 ... %d\n", SIMULATION_RX_PERBIT));
-	mcSHOW_DBG_MSG(("SIMULATION_TX_PERBIT		 ... %d\n", SIMULATION_TX_PERBIT));
-	mcSHOW_DBG_MSG(("\n\n"));
-
-	mcSHOW_DBG_MSG(("============== CTX before calibration ================\n"));
+	msg(CHK_INCLUDE_LOCAL_HEADER);
+
+	msg("SIMULATION_LP4_ZQ			 ... %d\n", SIMULATION_LP4_ZQ);
+	msg("SIMULATION_SW_IMPED		 ... %d\n", SIMULATION_SW_IMPED);
+	msg("SIMULATION_MIOCK_JMETER	 ... %d\n", SIMULATION_MIOCK_JMETER);
+	msg("SIMULATION_8PHASE			 ... %d\n", SIMULATION_8PHASE);
+	msg("SIMULATION_RX_INPUT_BUF	 ... %d\n", SIMULATION_RX_INPUT_BUF);
+	msg("SIMUILATION_CBT			 ... %d\n", SIMUILATION_CBT);
+	msg("SIMULATION_WRITE_LEVELING	 ... %d\n", SIMULATION_WRITE_LEVELING);
+	msg("SIMULATION_DUTY_CYC_MONITOR ... %d\n", SIMULATION_DUTY_CYC_MONITOR);
+	msg("SIMULATION_GATING			 ... %d\n", SIMULATION_GATING);
+	msg("SIMULATION_DATLAT			 ... %d\n", SIMULATION_DATLAT);
+	msg("SIMULATION_RX_RDDQC		 ... %d\n", SIMULATION_RX_RDDQC);
+	msg("SIMULATION_RX_PERBIT		 ... %d\n", SIMULATION_RX_PERBIT);
+	msg("SIMULATION_TX_PERBIT		 ... %d\n", SIMULATION_TX_PERBIT);
+	msg("\n\n");
+
+	msg("============== CTX before calibration ================\n");
 	dump_dramc_ctx(p);
 
 	DramcBroadcastOnOff(DRAMC_BROADCAST_OFF);
 
 	//vIO32Write4B_All2(p, DDRPHY_SHU_RK_CA_CMD1, 0x0FFF);
 	value = u4Dram_Register_Read(p, DRAMC_REG_DDRCOMMON0);
-	mcSHOW_DBG_MSG(("Get Addr:0x%x, Value:0x%x\n", DRAMC_REG_DDRCOMMON0, value));
+	msg("Get Addr:0x%x, Value:0x%x\n", DRAMC_REG_DDRCOMMON0, value);
 
 	value = u4Dram_Register_Read(p, DDRPHY_REG_SHU_RK_CA_CMD1);
-	mcSHOW_DBG_MSG(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_SHU_RK_CA_CMD1, value));
+	msg("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_SHU_RK_CA_CMD1, value);
 
 	value = u4Dram_Register_Read(p, DDRPHY_REG_MISC_DQO1);
-	mcSHOW_DBG_MSG(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_MISC_DQO1, value));
+	msg("Get Addr:0x%x, Value:0x%x\n", DDRPHY_REG_MISC_DQO1, value);
 
 	value = u4Dram_Register_Read(p, DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL );
-	mcSHOW_DBG_MSG(("Get Addr:0x%x, Value:0x%x\n", DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL, value));
+	msg("Get Addr:0x%x, Value:0x%x\n", DDRPHY_MD32_REG_SSPM_TIMER0_RESET_VAL, value);
 
 	DramcBroadcastOnOff(DRAMC_BROADCAST_ON); //LP4 broadcast on
 
@@ -2405,14 +2405,14 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
 	}
 
 #if (SIMULATION_SW_IMPED == 1)
-	mcSHOW_DBG_MSG(("\n----->DramcSwImpedanceCal begin...\n"));
+	msg("\n----->DramcSwImpedanceCal begin...\n");
 	timestamp_show();
 	// LP4 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266
 	// LP5 IMP_LOW_FREQ <= DDR3733, IMP_HIGH_FREQ >= DDR4266
 	DramcSwImpedanceCal(p, 1, IMP_LOW_FREQ);
 	DramcSwImpedanceCal(p, 1, IMP_HIGH_FREQ);
 	timestamp_show();
-	mcSHOW_DBG_MSG(("DramcSwImpedanceCal end<-----\n\n"));
+	msg("DramcSwImpedanceCal end<-----\n\n");
 #endif /* (SIMULATION_SW_IMPED == 1) */
 
 #if DV_SIMULATION_INIT_C
@@ -2429,7 +2429,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
 
 #ifdef DUMP_INIT_RG_LOG_TO_DE
 	#if 0 //Dump RG to other shuffle for FT used, don't delete
-		mcSHOW_DUMP_INIT_RG_MSG(("\n\n\n\n\n\n===== Save to Shuffle RG ======\n"));
+		mcSHOW_DUMP_INIT_RG_MSG("\n\n\n\n\n\n===== Save to Shuffle RG ======\n");
 		DramcSaveToShuffleReg(p, DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3);
 	#endif
 		while (1);
@@ -2440,20 +2440,20 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
 
 
 #if (SIMULATION_MIOCK_JMETER == 1)
-	mcSHOW_DBG_MSG(("\n----->DramcMiockJmeter begin...\n"));
+	msg("\n----->DramcMiockJmeter begin...\n");
 	timestamp_show();
 	PRE_MIOCK_JMETER_HQA_USED(p);
 	timestamp_show();
-	mcSHOW_DBG_MSG(("DramcMiockJmeter end<-----\n\n"));
+	msg("DramcMiockJmeter end<-----\n\n");
 #endif /* (SIMULATION_MIOCK_JMETER == 1) */
 
 #if (SIMULATION_8PHASE == 1)
 	if(is_lp5_family(p) && (p->frequency >= 2133)) {
-		mcSHOW_DBG_MSG(("\n----->Dramc8PhaseCal begin...\n"));
+		msg("\n----->Dramc8PhaseCal begin...\n");
 		timestamp_show();
 		Dramc8PhaseCal(p); // it must set before duty calib
 		timestamp_show();
-		mcSHOW_DBG_MSG(("Dramc8PhaseCal end<-----\n\n"));
+		msg("Dramc8PhaseCal end<-----\n\n");
 	}
 #endif /* (SIMULATION_8PHASE == 1) */
 
@@ -2486,11 +2486,11 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
 
 		#if (SIMULATION_8PHASE == 1)
 		if(is_lp5_family(p) && (p->frequency >= 2133)) {
-			mcSHOW_DBG_MSG(("\n----->Dramc8PhaseCal begin...\n"));
+			msg("\n----->Dramc8PhaseCal begin...\n");
 			timestamp_show();
 			Dramc8PhaseCal(p); // it must set before duty calib
 			timestamp_show();
-			mcSHOW_DBG_MSG(("Dramc8PhaseCal end<-----\n\n"));
+			msg("Dramc8PhaseCal end<-----\n\n");
 		}
 		#endif /* (SIMULATION_8PHASE == 1) */
 
@@ -2528,7 +2528,7 @@ DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
 	DramcModeRegReadByRank(p, RANK_0, 4, &u2val1);
 	DramcModeRegReadByRank(p, RANK_0, 5, &u2val2);
 	DramcModeRegReadByRank(p, RANK_0, 8, &u2val3);
-	mcSHOW_DBG_MSG(("[Runtime time MRR] MR4 = 0x%x, MR5 = 0x%x, MR8 = 0x%x\n", u2val1, u2val2, u2val3));
+	msg("[Runtime time MRR] MR4 = 0x%x, MR5 = 0x%x, MR8 = 0x%x\n", u2val1, u2val2, u2val3);
 #endif
 
 #if 0//DV_SIMULATION_DFS // NOTE: Don't use DramcDFSDirectJump_SPMMode. it will cause NULL object access.
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c
index 327f5caeb1..5fe1eef434 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_tracking.c
@@ -40,8 +40,8 @@ static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p)
 	// Backup rank, CKE fix on/off, HW MIOCK control settings
 	DramcBackupRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
 
-	mcSHOW_DBG_MSG3(("[ZQCalibration]\n"));
-	//mcFPRINTF((fp_A60501, "[ZQCalibration]\n"));
+	msg3("[ZQCalibration]\n");
+	//mcFPRINTF(fp_A60501, "[ZQCalibration]\n");
 
 	// Disable HW MIOCK control to make CLK always on
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL), 1, DRAMC_PD_CTRL_APHYCKCG_FIXOFF);
@@ -60,24 +60,24 @@ static DRAM_STATUS_T DramcStartDQSOSC_SWCMD(DRAMC_CTX_T *p)
 		u4TimeCnt --;
 		mcDELAY_US(1);	// Wait tZQCAL(min) 1us or wait next polling
 
-		mcSHOW_DBG_MSG3(("%d- ", u4TimeCnt));
-		//mcFPRINTF((fp_A60501, "%d- ", u4TimeCnt));
+		msg3("%d- ", u4TimeCnt);
+		//mcFPRINTF(fp_A60501, "%d- ", u4TimeCnt);
 	}while((u4Response==0) &&(u4TimeCnt>0));
 
 	vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SWCMD_EN), 0, SWCMD_EN_WCK2DQI_START_SWTRIG);
 
 	if(u4TimeCnt==0)//time out
 	{
-		mcSHOW_DBG_MSG(("ZQCAL Start fail (time out)\n"));
-		//mcFPRINTF((fp_A60501, "ZQCAL Start fail (time out)\n"));
+		msg("ZQCAL Start fail (time out)\n");
+		//mcFPRINTF(fp_A60501, "ZQCAL Start fail (time out)\n");
 		return DRAM_FAIL;
 	}
 
 	// Restore rank, CKE fix on, HW MIOCK control settings
 	DramcRestoreRegisters(p, u4RegBackupAddress, sizeof(u4RegBackupAddress)/sizeof(U32));
 
-	mcSHOW_DBG_MSG3(("\n[DramcZQCalibration] Done\n\n"));
-	//mcFPRINTF((fp_A60501, "\n[DramcZQCalibration] Done\n\n"));
+	msg3("\n[DramcZQCalibration] Done\n\n");
+	//mcFPRINTF(fp_A60501, "\n[DramcZQCalibration] Done\n\n");
 
 	return DRAM_OK;
 }
@@ -98,7 +98,7 @@ DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p)
 	U32 u4RegBak[2];
 
 #if MRW_CHECK_ONLY
-	mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+	mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
 
 	u4RegBak[0] = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_DRAMC_PD_CTRL));
@@ -138,7 +138,7 @@ DRAM_STATUS_T DramcDQSOSCAuto(DRAMC_CTX_T *p)
 		u2DQSOsc[1] = u1MR23 * 16 * 1000000 / (2 * u2DQSCnt * p->frequency); //tDQSOSC = 16*MR23*tCK/2*count
 	else
 		u2DQSOsc[1] = 0;
-	mcSHOW_DBG_MSG(("[DQSOSCAuto] RK%d, (LSB)MR18= 0x%x, (MSB)MR19= 0x%x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", u1GetRank(p), u2MR18, u2MR19, u2DQSOsc[0], u2DQSOsc[1]));
+	msg("[DQSOSCAuto] RK%d, (LSB)MR18= 0x%x, (MSB)MR19= 0x%x, tDQSOscB0 = %d ps tDQSOscB1 = %d ps\n", u1GetRank(p), u2MR18, u2MR19, u2DQSOsc[0], u2DQSOsc[1]);
 #endif
 
 	gu2MR18[p->channel][p->rank] = u2MR18;
@@ -174,9 +174,9 @@ DRAM_STATUS_T DramcDQSOSCMR23(DRAMC_CTX_T *p)
 		gu2DQSOSCTHRD_DEC[p->channel][p->rank] = (u1MR23 * u4tCK * u4tCK) / (u2DQSOSC * u2DQSOSC * 10);
 	}
 
-	mcSHOW_DBG_MSG(("CH%d_RK%d: MR19=0x%X, MR18=0x%X, DQSOSC=%d, MR23=%u, INC=%u, DEC=%u\n", p->channel, p->rank,
+	msg("CH%d_RK%d: MR19=0x%X, MR18=0x%X, DQSOSC=%d, MR23=%u, INC=%u, DEC=%u\n", p->channel, p->rank,
 					gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank], gu2DQSOSC[p->channel][p->rank],
-					u1MR23, gu2DQSOSCTHRD_INC[p->channel][p->rank], gu2DQSOSCTHRD_DEC[p->channel][p->rank]));
+					u1MR23, gu2DQSOSCTHRD_INC[p->channel][p->rank], gu2DQSOSCTHRD_DEC[p->channel][p->rank]);
 #endif
 	return DRAM_OK;
 }
@@ -201,8 +201,8 @@ DRAM_STATUS_T DramcDQSOSCSetMR18MR19(DRAMC_CTX_T *p)
 
 	vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_DQSOSC), P_Fld(u2DQSOscCnt[0], SHURK_DQSOSC_DQSOSC_BASE_RK0) | P_Fld(u2DQSOscCnt[1], SHURK_DQSOSC_DQSOSC_BASE_RK0_B1));
 
-	mcSHOW_DBG_MSG(("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]));
-	mcDUMP_REG_MSG(("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]));
+	msg("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]);
+	reg_msg("CH%d RK%d: MR19=%X, MR18=%X\n", p->channel, p->rank, gu2MR19[p->channel][p->rank], gu2MR18[p->channel][p->rank]);
 	return DRAM_OK;
 }
 
@@ -500,7 +500,7 @@ void DramcSWTxTracking(DRAMC_CTX_T *p)
 		DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_shuffleIndex(p, shuIdx);
 		if (pDstFreqTbl == NULL)
 		{
-			mcSHOW_ERR_MSG(("NULL pFreqTbl %d\n", shuIdx));
+			err("NULL pFreqTbl %d\n", shuIdx);
 			while (1);
 		}
 
@@ -511,11 +511,11 @@ void DramcSWTxTracking(DRAMC_CTX_T *p)
 		else
 		{
 			u1FreqRatioTX[shuIdx] = ((GetFreqBySel(p, pDstFreqTbl->freq_sel)) * 8) / p->frequency;
-			mcSHOW_DBG_MSG(("[SWTxTracking] ShuLevel=%d, Ratio[%d]=%d (%d, %d)\n", u1SRAMShuLevel, shuIdx, u1FreqRatioTX[shuIdx], GetFreqBySel(p, pDstFreqTbl->freq_sel), p->frequency));
+			msg("[SWTxTracking] ShuLevel=%d, Ratio[%d]=%d (%d, %d)\n", u1SRAMShuLevel, shuIdx, u1FreqRatioTX[shuIdx], GetFreqBySel(p, pDstFreqTbl->freq_sel), p->frequency);
 		}
 	}
 
-	mcSHOW_DBG_MSG(("[SWTxTracking] channel=%d\n", p->channel));
+	msg("[SWTxTracking] channel=%d\n", p->channel);
 	rankBak = u1GetRank(p);
 	shuBak = p->ShuRGAccessIdx;
 
@@ -583,9 +583,9 @@ void DramcSWTxTracking(DRAMC_CTX_T *p)
 				{
 					u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
 					u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] - (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
-					mcSHOW_DBG_MSG(("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d INC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
+					msg("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d INC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
 								, u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_INC[rankIdx]
-								, u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]));
+								, u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]);
 				}
 			}
 			else
@@ -596,9 +596,9 @@ void DramcSWTxTracking(DRAMC_CTX_T *p)
 				{
 					u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
 					u1UpdatedPI_DQM[shuIdx][rankIdx][byteIdx] = u1OriginalPI_DQM[shuIdx][rankIdx][byteIdx] + (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]);
-					mcSHOW_DBG_MSG(("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d DEC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
+					msg("SHU%u CH%d RK%d B%d, Base=%X Runtime=%X delta=%d DEC=%d PI=0x%B Adj=%d newPI=0x%B\n", shuIdx, p->channel, u1GetRank(p), byteIdx
 								, u2MR1819_Base[p->rank][byteIdx], u2MR1819_Runtime[p->rank][byteIdx], deltaMR1819, u2DQSOSC_DEC[rankIdx]
-								, u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]));
+								, u1OriginalPI_DQ[shuIdx][rankIdx][byteIdx], (u1AdjPI[rankIdx][byteIdx] * u1FreqRatioTX[shuIdx] / u1FreqRatioTX[u1SRAMShuLevel]), u1UpdatedPI_DQ[shuIdx][rankIdx][byteIdx]);
 				}
 			}
 		}
@@ -891,11 +891,11 @@ void DramcPrintRxDlyTrackDebugStatus(DRAMC_CTX_T *p)
 		p->channel = u1ChannelIdx;
 
 		u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO18));
-		//mcSHOW_DBG_MSG(("\nCH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m\n",u1ChannelIdx,u4value));
+		//msg("\nCH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m\n",u1ChannelIdx,u4value);
 		if (u4value & 1)
 		{
-			mcSHOW_DBG_MSG(("=== CH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m, %s %s shu: %d\n", u1ChannelIdx, u4value,
-						u4value & 0x2? "RK0: fail":"",u4value&0x4?"RK1: fail":"", (u4value >> 4) & 0x3));
+			msg("=== CH_%d DQ_RXDLY_TRRO18 = 0x\033[1;36m%x\033[m, %s %s shu: %d\n", u1ChannelIdx, u4value,
+						u4value & 0x2? "RK0: fail":"",u4value&0x4?"RK1: fail":"", (u4value >> 4) & 0x3);
 		}
 	}
 }
@@ -925,7 +925,7 @@ void DramcPrintRXDQDQSStatus(DRAMC_CTX_T *p, U8 u1Channel)
 	for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
 	{
 		vSetRank(p, u1RankIdx);
-		mcSHOW_DBG_MSG(("[RXDQDQSStatus] CH%d, RK%d\n", p->channel, u1RankIdx));
+		msg("[RXDQDQSStatus] CH%d, RK%d\n", p->channel, u1RankIdx);
 		if (u1RankIdx == 0)
 		u4ResultDQS_PI = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_MISC_DQ_RXDLY_TRRO22));
 		if (u1RankIdx == 1)
@@ -936,7 +936,7 @@ void DramcPrintRXDQDQSStatus(DRAMC_CTX_T *p, U8 u1Channel)
 		u1DQX_B1 = (u4ResultDQS_PI >> 16) & 0xff;
 		u1DQS1 = (u4ResultDQS_PI >> 24) & 0xff;
 
-		mcSHOW_DBG_MSG(("DQX_B0, DQS0, DQX_B1, DQS1 =(%d, %d, %d, %d)\n\n", u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1));
+		msg("DQX_B0, DQS0, DQX_B1, DQS1 =(%d, %d, %d, %d)\n\n", u1DQX_B0, u1DQS0, u1DQX_B1, u1DQS1);
 
 		}
 	vSetRank(p, backup_rank);
@@ -1012,8 +1012,8 @@ void DramcDummyReadAddressSetting(DRAMC_CTX_T *p)
 			dram_addr.rk = rankIdx;
 
 			get_dummy_read_addr(&dram_addr);
-			mcSHOW_DBG_MSG3(("=== dummy read address: CH_%d, RK%d, row: 0x%x, bk: %d, col: 0x%x\n\n",
-					channelIdx, rankIdx, dram_addr.row, dram_addr.bk, dram_addr.col));
+			msg3("=== dummy read address: CH_%d, RK%d, row: 0x%x, bk: %d, col: 0x%x\n\n",
+					channelIdx, rankIdx, dram_addr.row, dram_addr.bk, dram_addr.col);
 
 			vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_RK_DUMMY_RD_ADR2), P_Fld(dram_addr.row, RK_DUMMY_RD_ADR2_DMY_RD_ROW_ADR)
 																		| P_Fld(dram_addr.bk, RK_DUMMY_RD_ADR2_DMY_RD_BK));
@@ -1083,11 +1083,11 @@ void DramcDummyReadForTrackingEnable(DRAMC_CTX_T *p)
 	if (p->frequency >= 1600)
 	{
 		vIO32WriteFldMulti_All(DRAMC_REG_DUMMY_RD, P_Fld(1, DUMMY_RD_DMY_RD_RX_TRACK) | P_Fld(1, DUMMY_RD_DUMMY_RD_EN));
-		mcSHOW_DBG_MSG(("High Freq DUMMY_READ_FOR_TRACKING: ON\n"));
+		msg("High Freq DUMMY_READ_FOR_TRACKING: ON\n");
 	}
 	else
 	{
-		mcSHOW_DBG_MSG(("Low Freq DUMMY_READ_FOR_TRACKING: OFF\n"));
+		msg("Low Freq DUMMY_READ_FOR_TRACKING: OFF\n");
 	}
 
 	return;
@@ -1181,7 +1181,7 @@ void FreqJumpRatioCalculation(DRAMC_CTX_T *p)
 			DRAM_DFS_FREQUENCY_TABLE_T *pDstFreqTbl = get_FreqTbl_by_shuffleIndex(p, shuffle_dst_index);
 			if (pDstFreqTbl == NULL)
 			{
-				mcSHOW_ERR_MSG(("NULL pFreqTbl\n"));
+				err("NULL pFreqTbl\n");
 				#if __ETT__
 				while (1);
 				#endif
@@ -1197,12 +1197,12 @@ void FreqJumpRatioCalculation(DRAMC_CTX_T *p)
 				u2Freq = GetFreqBySel(p, pDstFreqTbl->freq_sel);
 				u2JumpRatio[jump_ratio_index] = divRoundClosest(u2Freq * 32, shuffle_src_freq);
 				//u2JumpRatio[jump_ratio_index] = (pDstFreqTbl->frequency/shuffle_src_freq)*32;
-				//mcSHOW_DBG_MSG3(("shuffle_%d=DDR%d / shuffle_%d=DDR%d \n", shuffle_dst_index, pFreqTbl->frequency<<1,
-				//															  shuffle_src_index, get_FreqTbl_by_shuffleIndex(p,shuffle_src_index)->frequency<<1));
-				//mcSHOW_DBG_MSG3(("Jump_RATIO_%d : 0x%x\n", jump_ratio_index, u2JumpRatio[jump_ratio_index],
-				//											  get_FreqTbl_by_shuffleIndex(p,shuffle_src_index)->frequency));
+				//msg3("shuffle_%d=DDR%d / shuffle_%d=DDR%d \n", shuffle_dst_index, pFreqTbl->frequency<<1,
+				//															  shuffle_src_index, get_FreqTbl_by_shuffleIndex(p,shuffle_src_index)->frequency<<1);
+				//msg3("Jump_RATIO_%d : 0x%x\n", jump_ratio_index, u2JumpRatio[jump_ratio_index],
+				//											  get_FreqTbl_by_shuffleIndex(p,shuffle_src_index)->frequency);
 			}
-			mcSHOW_DBG_MSG3(("Jump_RATIO [%d]: %x\tFreq %d -> %d\tDDR%d -> DDR%d\n", jump_ratio_index, u2JumpRatio[jump_ratio_index], get_shuffleIndex_by_Freq(p), shuffle_dst_index, shuffle_src_freq << 1, u2Freq << 1));
+			msg3("Jump_RATIO [%d]: %x\tFreq %d -> %d\tDDR%d -> DDR%d\n", jump_ratio_index, u2JumpRatio[jump_ratio_index], get_shuffleIndex_by_Freq(p), shuffle_dst_index, shuffle_src_freq << 1, u2Freq << 1);
 			jump_ratio_index++;
 		}
 	}
@@ -1246,7 +1246,7 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)
 		mck2ui = 2; /* 1: 4 mode */
 #endif
 
-	mcSHOW_DBG_MSG(("Pre-setting of DQS Precalculation\n"));
+	msg("Pre-setting of DQS Precalculation\n");
 
 	for (byte_idx = 0; byte_idx < (p->data_width / DQS_BIT_NUMBER); byte_idx++) {
 		for (rank = RANK_0; rank < p->support_rank_num; rank++) {
@@ -1326,8 +1326,8 @@ void DramcDQSPrecalculation_preset(DRAMC_CTX_T *p)//Test tDQSCK_temp Pre-calcula
 	U32 u1Delay_Addr[2] = {0}, u1Delay_Fld[2];
 	REG_FLD_DQS_PRE_K TransferReg;
 
-	mcSHOW_DBG_MSG(("Pre-setting of DQS Precalculation\n"));
-	mcDUMP_REG_MSG(("Pre-setting of DQS Precalculation\n"));
+	msg("Pre-setting of DQS Precalculation\n");
+	reg_msg("Pre-setting of DQS Precalculation\n");
 
 	if ((u1ShuLevel >= SRAM_SHU4) && (u1ShuLevel <= SRAM_SHU7))
 	{ //SHU4, 5, 6, 7
@@ -1557,7 +1557,7 @@ void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel)
 	for (u1RankIdx = 0; u1RankIdx < u1RankMax; u1RankIdx++)
 	{
 		vSetRank(p, u1RankIdx);
-		mcSHOW_DBG_MSG(("[DramcHWGatingStatus] Channel=%d, Rank=%d\n", p->channel, u1RankIdx));
+		msg("[DramcHWGatingStatus] Channel=%d, Rank=%d\n", p->channel, u1RankIdx);
 
 		u1Dqs_pi[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B0_RK0),
 			GATING_ERR_LATCH_DLY_B0_RK0_DQSIEN0_PI_DLY_RK0);
@@ -1573,10 +1573,10 @@ void DramcPrintHWGatingStatus(DRAMC_CTX_T *p, U8 u1Channel)
 		u1Dqs_ui_P1[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_GATING_ERR_LATCH_DLY_B1_RK0),
 			GATING_ERR_LATCH_DLY_B1_RK0_DQSIEN1_UI_P1_DLY_RK0);;
 
-		mcSHOW_DBG_MSG(("Byte0(ui, pi) =(%d, %d)\n Byte1(ui, pi) =(%d, %d)\n",
-			u1Dqs_ui[0], u1Dqs_pi[0], u1Dqs_ui[1], u1Dqs_pi[1]));
-		mcSHOW_DBG_MSG(("UI_Phase1 (DQS0~3) =(%d, %d, %d, %d)\n\n",
-			u1Dqs_ui_P1[0], u1Dqs_ui_P1[1], u1Dqs_ui_P1[2], u1Dqs_ui_P1[3]));
+		msg("Byte0(ui, pi) =(%d, %d)\n Byte1(ui, pi) =(%d, %d)\n",
+			u1Dqs_ui[0], u1Dqs_pi[0], u1Dqs_ui[1], u1Dqs_pi[1]);
+		msg("UI_Phase1 (DQS0~3) =(%d, %d, %d, %d)\n\n",
+			u1Dqs_ui_P1[0], u1Dqs_ui_P1[1], u1Dqs_ui_P1[2], u1Dqs_ui_P1[3]);
 	}
 
 	vSetRank(p, backup_rank);
@@ -1622,10 +1622,10 @@ void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
 
 		u1ShuffleLevel = u4IO32ReadFldAlign(DRAMC_REG_SHUSTATUS, SHUSTATUS_SHUFFLE_LEVEL);
 
-		mcSHOW_DBG_MSG3(("\n[HWGatingTrackingRecord] Channel=%d, Rank=%d, SHU_LEVEL=%d\n", p->channel, u1RankIdx, u1ShuffleLevel));
+		msg3("\n[HWGatingTrackingRecord] Channel=%d, Rank=%d, SHU_LEVEL=%d\n", p->channel, u1RankIdx, u1ShuffleLevel);
 
-		mcSHOW_DBG_MSG3(("Run Time HW Gating Debug Information :\n"));
-		mcSHOW_DBG_MSG3(("		  B0=(DFS,Lead,Lag,4T, UI, PI), B1=(DFS,Lead,Lag,4T, UI, PI)\n"));
+		msg3("Run Time HW Gating Debug Information :\n");
+		msg3("		  B0=(DFS,Lead,Lag,4T, UI, PI), B1=(DFS,Lead,Lag,4T, UI, PI)\n");
 
 		for (u1Info_NUM = 0; u1Info_NUM < u1Info_Max_MUM; u1Info_NUM++)
 		{
@@ -1652,16 +1652,16 @@ void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
 
 		  if (u1Info_NUM < 10)
 		  {
-			mcSHOW_DBG_MSG3(("Info= %d ", u1Info_NUM));
+			msg3("Info= %d ", u1Info_NUM);
 		  }
 		  else
 		  {
-			mcSHOW_DBG_MSG3(("Info=%d ", u1Info_NUM));
+			msg3("Info=%d ", u1Info_NUM);
 		  }
 
-		  mcSHOW_DBG_MSG3(("B0=(  %d,  %d,	%d,  %d,  %d, %d), B1=(  %d,  %d,  %d,	%d,  %d,  %d)\n",
+		  msg3("B0=(  %d,  %d,	%d,  %d,  %d, %d), B1=(  %d,  %d,  %d,	%d,  %d,  %d)\n",
 		  u1DBG_Dqs0_DFS, u1DBG_Dqs0_Lead, u1DBG_Dqs0_Lag, u1DBG_Dqs0_UI / 8, u1DBG_Dqs0_UI % 8, u1DBG_Dqs0_PI,
-		  u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI / 8, u1DBG_Dqs1_UI % 8, u1DBG_Dqs1_PI));
+		  u1DBG_Dqs1_DFS, u1DBG_Dqs1_Lead, u1DBG_Dqs1_Lag, u1DBG_Dqs1_UI / 8, u1DBG_Dqs1_UI % 8, u1DBG_Dqs1_PI);
 		}
 
 		//Run Time HW Gating Max and Min Value Record
@@ -1681,12 +1681,12 @@ void DramcHWGatingTrackingRecord(DRAMC_CTX_T *p, U8 u1Channel)
 		u2Dqs1_UI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 6) & 0x3f;
 		u2Dqs1_PI_MIN_DLY = (u4Dqs1_MAX_MIN_DLY >> 0) & 0x3f;
 
-		mcSHOW_DBG_MSG3(("B0 = MAX(4T, UI, PI) MIN(4T, UI, PI), B1 = MAX(4T, UI, PI) MIN(4T, UI, PI)\n"));
-		mcSHOW_DBG_MSG3(("B0 = MAX( %d,  %d, %d) MIN( %d,  %d, %d),  B1 = MAX( %d,	%d, %d) MIN( %d,  %d, %d)\n",
+		msg3("B0 = MAX(4T, UI, PI) MIN(4T, UI, PI), B1 = MAX(4T, UI, PI) MIN(4T, UI, PI)\n");
+		msg3("B0 = MAX( %d,  %d, %d) MIN( %d,  %d, %d),  B1 = MAX( %d,	%d, %d) MIN( %d,  %d, %d)\n",
 						u2Dqs0_UI_MAX_DLY / 8, u2Dqs0_UI_MAX_DLY % 8, u2Dqs0_PI_MAX_DLY,
 						u2Dqs0_UI_MIN_DLY / 8, u2Dqs0_UI_MIN_DLY % 8, u2Dqs0_PI_MIN_DLY,
 						u2Dqs1_UI_MAX_DLY / 8, u2Dqs1_UI_MAX_DLY % 8, u2Dqs1_PI_MAX_DLY,
-						u2Dqs1_UI_MIN_DLY / 8, u2Dqs1_UI_MIN_DLY % 8, u2Dqs1_PI_MIN_DLY));
+						u2Dqs1_UI_MIN_DLY / 8, u2Dqs1_UI_MIN_DLY % 8, u2Dqs1_PI_MIN_DLY);
 	}
 	vSetRank(p, u1RankBak);
 	p->channel = u1ChannelBak;
@@ -1715,7 +1715,7 @@ void DramcPrintRXFIFODebugStatus(DRAMC_CTX_T *p)
 		u4value = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_STBERR_RK0_R)) & (0xf << 24); //DDRPHY NAO bit24~27
 		if (u4value)
 		{
-			mcSHOW_DBG_MSG(("\n[RXFIFODebugStatus] CH_%d MISC_STBERR_RK0_R_RX_ARDQ = 0x\033[1;36m%x\033[m for Gating error information\n", u1ChannelIdx, u4value));
+			msg("\n[RXFIFODebugStatus] CH_%d MISC_STBERR_RK0_R_RX_ARDQ = 0x\033[1;36m%x\033[m for Gating error information\n", u1ChannelIdx, u4value);
 		}
 	}
 	p->channel = u1ChannelBak;
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c
index e10f729637..1f1ec2d3d3 100644
--- a/src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c
+++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_utility.c
@@ -39,7 +39,7 @@ u8 is_heff_mode(DRAMC_CTX_T *p)
 {
 	u8 res = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SHU_COMMON0),
 			SHU_COMMON0_LP5HEFF_MODE);
-	mcSHOW_DBG_MSG5(("HEFF Mode: %d\n", res));
+	msg5("HEFF Mode: %d\n", res);
 	return res? TRUE: FALSE;
 }
 
@@ -120,13 +120,13 @@ void DramcBroadcastOnOff(U32 bOnOff)
 			if (bOnOff)
 			{
 				broadcast_on();
-				mcSHOW_DBG_MSG(("Broadcast ON\n"));
+				msg("Broadcast ON\n");
 				u1BroadcastOnOff = bOnOff;
 			}
 			else
 			{
 				broadcast_off();
-				mcSHOW_DBG_MSG(("Broadcast OFF\n"));
+				msg("Broadcast OFF\n");
 				u1BroadcastOnOff = bOnOff;
 			}
 		}
@@ -142,7 +142,7 @@ void DramcBroadcastOnOff(U32 bOnOff)
 			val = bOnOff;
 			// *((volatile unsigned int *)(DRAMC_WBR)) = bOnOff;
 
-			mcSHOW_DUMP_INIT_RG_MSG(("*((UINT32P)(0x%x)) = 0x%x;\n",addr, val));
+			mcSHOW_DUMP_INIT_RG_MSG("*(UINT32P)(0x%x)) = 0x%x;\n",addr, val);
 	//		  mcDELAY_MS(1);
 #if (FOR_DV_SIMULATION_USED==0)
 			GPT_Delay_ms(1);
@@ -188,14 +188,14 @@ void CheckDramcWBR(U32 u4address)
 		#endif
 		if ((((u4address - Channel_A_DRAMC_NAO_BASE_VIRTUAL) >> POS_BANK_NUM) & channel_and_value) != CHANNEL_A)
 		{
-			mcSHOW_ERR_MSG(("Error! virtual address 0x%x is not CHA and cannot use Dramc WBR\n", u4address));
+			err("Error! virtual address 0x%x is not CHA and cannot use Dramc WBR\n", u4address);
 			while (1);
 		}
 			for (i = 0; i < CANNOT_USE_WBR_SIZE; i++)
 			{
 				if (u4Cannot_Use_Dramc_WBR_Reg[i] == u4address)
 				{
-					mcSHOW_ERR_MSG(("Error! virtual address 0x%x cannot use Dramc WBR\n", u4address));
+					err("Error! virtual address 0x%x cannot use Dramc WBR\n", u4address);
 					while (1);
 				}
 			 }
@@ -359,7 +359,7 @@ static void setFreqGroup(DRAMC_CTX_T *p)
 		}
 	}
 
-	mcSHOW_DBG_MSG3(("[setFreqGroup] p-> frequency %u, freqGroup: %u\n", p->frequency, p->freqGroup));
+	msg3("[setFreqGroup] p-> frequency %u, freqGroup: %u\n", p->frequency, p->freqGroup);
 	return;
 }
 
@@ -399,8 +399,8 @@ void GetPhyPllFrequency(DRAMC_CTX_T *p)
 	if (u1SopenDQ == ENABLE) // for 1:4 mode DDR800 (3.2G/DIV4)
 		u4DataRate >>= 2;
 
-	//mcSHOW_DBG_MSG(("PCW=0x%X, u4PREDIV=%d, u4POSDIV=%d, CKDIV4=%d, DataRate=%d\n", u4SDM_PCW, u4PREDIV, u4POSDIV, u4CKDIV4, u4DataRate));
-	mcSHOW_DBG_MSG(("[F] DataRate=%d at SHU%d\n", u4DataRate, u1ShuLevel));
+	//msg("PCW=0x%X, u4PREDIV=%d, u4POSDIV=%d, CKDIV4=%d, DataRate=%d\n", u4SDM_PCW, u4PREDIV, u4POSDIV, u4CKDIV4, u4DataRate);
+	msg("[F] DataRate=%d at SHU%d\n", u4DataRate, u1ShuLevel);
 }
 #endif
 
@@ -484,14 +484,14 @@ DRAM_CBT_MODE_T vGet_Dram_CBT_Mode(DRAMC_CTX_T *p)
 void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p)
 {
 #if __ETT__
-	mcSHOW_DBG_MSG(("===============================================================================\n"
+	msg("===============================================================================\n"
 					"Dram Type= %d, Freq= %u, FreqGroup= %u, CH_%d, rank %d\n"
 					"fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n"
 					"===============================================================================\n",
 						p->dram_type, DDRPhyFMeter()?DDRPhyFMeter():p->frequency, p->freqGroup, p->channel, p->rank,
-						p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p)));
+						p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p));
 #else
-	mcSHOW_DBG_MSG(("==\n"
+	msg("==\n"
 					"Dram Type= %d, Freq= %u, CH_%d, rank %d\n"
 					"fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n"
 					"==\n",
@@ -502,34 +502,34 @@ void vPrintCalibrationBasicInfo(DRAMC_CTX_T *p)
 						p->dram_fsp,
 						p->odt_onoff,
 						p->dram_cbt_mode[p->rank],
-						vGet_Div_Mode(p)));
+						vGet_Div_Mode(p));
 #endif
 }
 
 #if VENDER_JV_LOG
 void vPrintCalibrationBasicInfo_ForJV(DRAMC_CTX_T *p)
 {
-	mcSHOW_DBG_MSG5(("\n\nDram type:"));
+	msg5("\n\nDram type:");
 
 	switch (p->dram_type)
 	{
 		case TYPE_LPDDR4:
-			mcSHOW_DBG_MSG5(("LPDDR4\t"));
+			msg5("LPDDR4\t");
 			break;
 
 		case TYPE_LPDDR4X:
-			mcSHOW_DBG_MSG5(("LPDDR4X\t"));
+			msg5("LPDDR4X\t");
 			break;
 
 		case TYPE_LPDDR4P:
-			mcSHOW_DBG_MSG5(("LPDDR4P\t"));
+			msg5("LPDDR4P\t");
 			break;
 	}
 
-	mcSHOW_DBG_MSG5(("Freq: %d, FreqGroup %u, channel %d, rank %d\n"
+	msg5("Freq: %d, FreqGroup %u, channel %d, rank %d\n"
 					 "dram_fsp= %d, odt_onoff= %d, Byte mode= %d, DivMode= %d\n\n",
 										p->frequency, p->freqGroup, p->channel, p->rank,
-										p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p)));
+										p->dram_fsp, p->odt_onoff, p->dram_cbt_mode[p->rank], vGet_Div_Mode(p));
 
 	return;
 }
@@ -607,7 +607,7 @@ U16 GetFreqBySel(DRAMC_CTX_T *p, DRAM_PLL_FREQ_SEL_T sel)
 			break;
 
 		default:
-			mcSHOW_ERR_MSG(("[GetFreqBySel] freq sel is incorrect !!!\n"));
+			err("[GetFreqBySel] freq sel is incorrect !!!\n");
 			break;
 	}
 
@@ -651,7 +651,7 @@ DRAM_PLL_FREQ_SEL_T GetSelByFreq(DRAMC_CTX_T *p, U16 u2freq)
 			sel=LP4_DDR400;
 			break;
 		default:
-			mcSHOW_ERR_MSG(("[GetSelByFreq] sel is incorrect !!!\n"));
+			err("[GetSelByFreq] sel is incorrect !!!\n");
 			break;
 	}
 
@@ -769,7 +769,7 @@ void DramcWriteDBIOnOff(DRAMC_CTX_T *p, U8 onoff)
 {
 	// DRAMC Write-DBI On/Off
 	vIO32WriteFldAlign_All(DRAMC_REG_SHU_TX_SET0, onoff, SHU_TX_SET0_DBIWR);
-	mcSHOW_DBG_MSG(("DramC Write-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off")));
+	msg("DramC Write-DBI %s\n", (onoff == DBI_ON) ? "on" : "off");
 }
 
 void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff)
@@ -777,15 +777,15 @@ void DramcReadDBIOnOff(DRAMC_CTX_T *p, U8 onoff)
 	// DRAMC Read-DBI On/Off
 	vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B0_DQ7, onoff, SHU_B0_DQ7_R_DMDQMDBI_SHU_B0);
 	vIO32WriteFldAlign_All(DDRPHY_REG_SHU_B1_DQ7, onoff, SHU_B1_DQ7_R_DMDQMDBI_SHU_B1);
-	mcSHOW_DBG_MSG(("DramC Read-DBI %s\n", ((onoff == DBI_ON) ? "on" : "off")));
+	msg("DramC Read-DBI %s\n", (onoff == DBI_ON) ? "on" : "off");
 }
 #if ENABLE_READ_DBI
 void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff)
 {
 #if MRW_CHECK_ONLY
-	mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+	mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
-	//mcSHOW_DBG_MSG(("--Fsp%d --\n", p->dram_fsp));
+	//msg("--Fsp%d --\n", p->dram_fsp);
 
 	//DRAM MR3[6] read-DBI On/Off
 	u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0xbf) | (onoff << 6));
@@ -797,7 +797,7 @@ void SetDramModeRegForReadDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff)
 void SetDramModeRegForWriteDBIOnOff(DRAMC_CTX_T *p, U8 u1fsp, U8 onoff)
 {
 #if MRW_CHECK_ONLY
-	mcSHOW_MRW_MSG(("\n==[MR Dump] %s==\n", __func__));
+	mcSHOW_MRW_MSG("\n==[MR Dump] %s==\n", __func__);
 #endif
 	//DRAM MR3[7] write-DBI On/Off
 	u1MR03Value[u1fsp] = ((u1MR03Value[u1fsp] & 0x7F) | (onoff << 7));
@@ -941,7 +941,7 @@ static void DramcSetRWOFOEN(DRAMC_CTX_T *p, U8 u1onoff)
 
 			if(u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
 			{
-				mcSHOW_ERR_MSG(("RWOFOEN timout! queue is not empty\n"));
+				err("RWOFOEN timout! queue is not empty\n");
 			#if __ETT__
 				while(1);
 			#else
@@ -1134,14 +1134,14 @@ static void DramcEngine2CheckComplete(DRAMC_CTX_T *p, U8 u1status)
 		u4loop_count++;
 		if ((u4loop_count > 3) && (u4loop_count <= MAX_CMP_CPT_WAIT_LOOP))
 		{
-			//mcSHOW_ERR_MSG(("TESTRPT_DM_CMP_CPT: %d\n", u4loop_count));
+			//err("TESTRPT_DM_CMP_CPT: %d\n", u4loop_count);
 		}
 		else if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
 		{
 			/*TINFO="fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count*/
-			mcSHOW_DBG_MSG(("fcWAVEFORM_MEASURE_A %d :time out, [22:20]=0x%x\n", u4loop_count, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));
+			msg("fcWAVEFORM_MEASURE_A %d :time out, [22:20]=0x%x\n", u4loop_count, u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT));
 
-			//mcFPRINTF((fp_A60501, "fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count));
+			//mcFPRINTF(fp_A60501, "fcWAVEFORM_MEASURE_A %d: time out\n", u4loop_count);
 
 			break;
 		}
@@ -1156,7 +1156,7 @@ static void DramcEngine2CheckComplete(DRAMC_CTX_T *p, U8 u1status)
 			u4loop_count++;
 			if(u4loop_count > MAX_CMP_CPT_WAIT_LOOP)
 			{
-				mcSHOW_DBG_MSG(("over MAX_CMP_CPT_WAIT_LOOP[%d] TEST_LOOP_CNT[%d]\n", u4loop_count, u4Ta2_loop_count));
+				msg("over MAX_CMP_CPT_WAIT_LOOP[%d] TEST_LOOP_CNT[%d]\n", u4loop_count, u4Ta2_loop_count);
 				break;
 			}
 		}
@@ -1236,7 +1236,7 @@ DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1Te
 	// error handling
 	if (!p)
 	{
-		mcSHOW_ERR_MSG(("context is NULL\n"));
+		err("context is NULL\n");
 		return DRAM_FAIL;
 	}
 
@@ -1244,7 +1244,7 @@ DRAM_STATUS_T DramcEngine2Init(DRAMC_CTX_T *p, U32 test2_1, U32 test2_2, U8 u1Te
 //	  if ((u1LoopCnt > 15) || (u1LoopCnt < 0))		// U8 >=0 always.
 	if (u1LoopCnt > 15)
 	{
-		mcSHOW_ERR_MSG(("wrong param: u1LoopCnt > 15\n"));
+		err("wrong param: u1LoopCnt > 15\n");
 		return DRAM_FAIL;
 	}
 
@@ -1495,17 +1495,17 @@ void TA2_Test_Run_Time_HW_Presetting(DRAMC_CTX_T * p, U32 len, TA2_RKSEL_TYPE_T
 	{
 		// In order to enhance XRT R2R/W2W probability, use TEST2_4_TESTAGENTRKSEL=3, PERFCTL0_RWOFOEN=0 mode
 		uiRWOFOEN = 0;
-		mcSHOW_DBG_MSG(("=== TA2 XRT R2R/W2W\n"));
+		msg("=== TA2 XRT R2R/W2W\n");
 	}
 	else
 	{
 		uiRWOFOEN = 1;
 #if !ENABLE_EMI_LPBK_TEST
-		mcSHOW_DBG_MSG(("=== TA2 HW\n"));
+		msg("=== TA2 HW\n");
 #endif
 	}
 #if !ENABLE_EMI_LPBK_TEST
-	mcSHOW_DBG_MSG(("=== OFFSET:0x%x\n", u4Offset));
+	msg("=== OFFSET:0x%x\n", u4Offset);
 #endif
 	for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
 	{
@@ -1540,7 +1540,7 @@ void TA2_Test_Run_Time_Pat_Setting(DRAMC_CTX_T *p, U8 PatSwitch)
 	if (u1loop || PatSwitch == TA2_PAT_SWITCH_ON)
 	{
 #if !ENABLE_EMI_LPBK_TEST
-		mcSHOW_DBG_MSG(("TA2 PAT: %d\n", u1Pat));
+		msg("TA2 PAT: %d\n", u1Pat);
 #endif
 		for (u1ChannelIdx = CHANNEL_A; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
 		{
@@ -1573,7 +1573,7 @@ void TA2_Test_Run_Time_HW_Write(DRAMC_CTX_T * p, U8 u1Enable)
 	U8 u1ChannelIdx;
 
 #if !ENABLE_EMI_LPBK_TEST
-	mcSHOW_DBG_MSG(("\nTA2 Trigger Write\n"));
+	msg("\nTA2 Trigger Write\n");
 #endif
 	for (u1ChannelIdx = 0; u1ChannelIdx < p->support_channel_num; u1ChannelIdx++)
 	{
@@ -1594,12 +1594,12 @@ static void TA2_Show_Cnt(DRAMC_CTX_T * p, U32 u4ErrorValue)
 		if (u4ErrorValue & (1 << u1RankIdx))
 		{
 			err_count++;
-			mcSHOW_DBG_MSG(("HW channel(%d) Rank(%d), TA2 failed, pass_cnt:%d, err_cnt:%d\n", p->channel, u1RankIdx, pass_count, err_count));
+			msg("HW channel(%d) Rank(%d), TA2 failed, pass_cnt:%d, err_cnt:%d\n", p->channel, u1RankIdx, pass_count, err_count);
 		}
 		else
 		{
 			pass_count++;
-			mcSHOW_DBG_MSG(("HW channel(%d) Rank(%d), TA2 pass, pass_cnt:%d, err_cnt:%d\n", p->channel, u1RankIdx, pass_count, err_count));
+			msg("HW channel(%d) Rank(%d), TA2 pass, pass_cnt:%d, err_cnt:%d\n", p->channel, u1RankIdx, pass_count, err_count);
 		}
 	}
 }
@@ -1616,9 +1616,9 @@ U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)
 		u4ErrorValue = DramcEngine2Compare(p, TE_OP_WRITE_READ_CHECK);
 		if (u4ErrorValue & 0x3) //RK0 or RK1 test fail
 		{
-			mcSHOW_DBG_MSG(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))));
+			msg("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)));
 #if defined(SLT)
-			mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000, line: %d\n",__LINE__));
+			err("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000, line: %d\n",__LINE__);
 			while (1);
 #endif
 		}
@@ -1646,7 +1646,7 @@ U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)
 	{
 		vSetPHY2ChannelMapping(p, u1ChannelIdx);
 		u4Ta2LoopEn = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), TEST2_A0_TA2_LOOP_EN);
-		//mcSHOW_DBG_MSG(("### u4Ta2LoopEn:%d ### \n", u4Ta2LoopEn));
+		//msg("### u4Ta2LoopEn:%d ### \n", u4Ta2LoopEn);
 
 		if(u4Ta2LoopEn)
 		{
@@ -1656,7 +1656,7 @@ U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)
 
 			vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TEST2_A0), 0, TEST2_A0_LOOP_NV_END);//cancel NV_END
 			DramcEngine2CheckComplete(p, u1status);//Wait for complete
-			//mcSHOW_DBG_MSG(("TESTRPT_TESTSTAT:%x\n", u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT)));//check TESTRPT_TESTSTAT
+			//msg("TESTRPT_TESTSTAT:%x\n", u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT), TESTRPT_TESTSTAT));//check TESTRPT_TESTSTAT
 			u4ErrorValue = (u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_TESTRPT)) >> 4) & 0x3; //CMP_ERR_RK0/1
 		}
 		else
@@ -1664,9 +1664,9 @@ U32 TA2_Test_Run_Time_HW_Status(DRAMC_CTX_T * p)
 
 		if (u4ErrorValue & 0x3) //RK0 or RK1 test fail
 		{
-			mcSHOW_DBG_MSG(("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR))));
+			msg("=== HW channel(%d) u4ErrorValue: 0x%x, bit error: 0x%x\n", u1ChannelIdx, u4ErrorValue, u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_CMP_ERR)));
 #if defined(SLT)
-			mcSHOW_ERR_MSG(("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000, line: %d\n",__LINE__));
+			err("[dramc] DRAM_FATAL_ERR_FLAG = 0x80000000, line: %d\n",__LINE__);
 			while (1);
 #endif
 		}
@@ -1724,7 +1724,7 @@ static U8 *DramcFetchGlobalMR(DRAMC_CTX_T *p, U8 mr_idx)
 		case 26: pMRGlobalValue = &u1MR26Value[p->rank]; break;
 		case 30: pMRGlobalValue = &u1MR30Value[p->rank]; break;
 		default:
-			mcSHOW_ERR_MSG(("%s NULL\n", __func__));
+			err("%s NULL\n", __func__);
 			#if __ETT__
 			while(1);
 			#endif
@@ -2004,7 +2004,7 @@ U8 DramcMRWriteBackup(DRAMC_CTX_T *p, U8 u1MRIdx, U8 u1Rank)
 	if (u1MRBackup_ERR_Flag==0)
 	{
 		u1Value=u4IO32ReadFldAlign(DRAMC_REG_ADDR(TransferReg.u4Addr), TransferReg.u4Fld);
-		mcSHOW_MRW_MSG(("  [MRW Backup] Rank%d FSP%d MR%d=0x%x\n",u1Rank, gFSPWR_Flag[u1Rank], u1MRIdx, u1Value));
+		mcSHOW_MRW_MSG("  [MRW Backup] Rank%d FSP%d MR%d=0x%x\n",u1Rank, gFSPWR_Flag[u1Rank], u1MRIdx, u1Value);
 	}
 	vSetRank(p, u1backupRK);
 
@@ -2075,7 +2075,7 @@ void DramcModeRegRead(DRAMC_CTX_T *p, U8 u1MRIdx, U16 *u2pValue)
 	gDUMP_INIT_RG_LOG_TO_DE_RG_log_flag=1;
 #endif
 
-	mcSHOW_DBG_MSG3(("Read MR%d =0x%x\n", u1MRIdx, u4MRValue));
+	msg3("Read MR%d =0x%x\n", u1MRIdx, u4MRValue);
 }
 
 
@@ -2171,7 +2171,7 @@ void DramcModeRegWriteByRank_RTMRW(DRAMC_CTX_T *p, U8 *u1Rank, U8 *u1MRIdx, U8 *
 
 	if (u4TimeCnt == 0)//time out
 	{
-		mcSHOW_DBG_MSG(("[LP5 RT MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank[0], u1MRIdx[0], u1Value[0]));
+		msg("[LP5 RT MRW ] Resp fail (time out) Rank=%d, MR%d=0x%x\n", u1Rank[0], u1MRIdx[0], u1Value[0]);
 	}
 
 #if __LP5_COMBO__
@@ -2217,7 +2217,7 @@ static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx,
 	while (u4IO32ReadFldAlign(DRAMC_REG_ADDR(DRAMC_REG_SPCMDRESP), SPCMDRESP_MRW_RESPONSE) == 0)
 	{
 		counter++;
-		mcSHOW_DBG_MSG2(("wait MRW command Rank%d MR%d =0x%x fired (%d)\n", u1Rank, u1MRIdx, u1Value, counter));
+		msg2("wait MRW command Rank%d MR%d =0x%x fired (%d)\n", u1Rank, u1MRIdx, u1Value, counter);
 		mcDELAY_US(1);
 	}
 
@@ -2233,12 +2233,12 @@ static void DramcModeRegWriteByRank_SCSM(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx,
 
 void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
 {
-	mcSHOW_DBG_MSG2(("MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value));
+	msg2("MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value);
 
 #ifndef ENABLE_POST_PACKAGE_REPAIR
 	if ((u1MRIdx == 0x04) && (u1Value & 0x10))
 	{
-		mcSHOW_ERR_MSG(("ERROR MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value));
+		err("ERROR MRW RK%d MR#%d = 0x%x\n", u1Rank,u1MRIdx, u1Value);
 		while(1);
 	}
 #endif
@@ -2308,20 +2308,20 @@ void DramcModeRegWriteByRank(DRAMC_CTX_T *p, U8 u1Rank, U8 u1MRIdx, U8 u1Value)
 		if(u1PrintModeRegWrite)
 		{
 			#if VENDER_JV_LOG
-			mcSHOW_JV_LOG_MSG(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
+			jv_msg("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value);
 			#endif
 			#if MRW_CHECK_ONLY
-			mcSHOW_MRW_MSG(("MRW CH%d Rank%d FSP%d MR%d =0x%x\n", p->channel, u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, u1Value));
+			mcSHOW_MRW_MSG("MRW CH%d Rank%d FSP%d MR%d =0x%x\n", p->channel, u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, u1Value);
 			#endif
-			mcSHOW_DBG_MSG2(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
-			mcDUMP_REG_MSG(("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value));
+			msg2("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value);
+			reg_msg("Write Rank%d MR%d =0x%x\n", u1RankIdx, u1MRIdx, u1Value);
 		}
 		#if MRW_BACKUP
 		U8 MR_backup;
 
 			MR_backup=DramcMRWriteBackup(p, u1MRIdx, u1RankIdx);
 			if (MR_backup!=0xff)
-			mcSHOW_MRW_MSG(("  [MRW Check] Rank%d FSP%d Backup_MR%d= 0x%x MR%d= 0x%x ==>%s\n", u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, MR_backup, u1MRIdx, u1Value, (u1Value==MR_backup?"PASS":"FAIL")));
+			mcSHOW_MRW_MSG("  [MRW Check] Rank%d FSP%d Backup_MR%d= 0x%x MR%d= 0x%x ==>%s\n", u1RankIdx, gFSPWR_Flag[u1RankIdx], u1MRIdx, MR_backup, u1MRIdx, u1Value, (u1Value==MR_backup?"PASS":"FAIL"));
 		#endif
 
 		#if (__LP5_COMBO__ == TRUE)
@@ -2352,7 +2352,7 @@ void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num)
 #ifdef __ETT__
 	if (backup_num > 100 || u1gpRegBackup)
 	{
-		mcSHOW_ERR_MSG(("[DramcBackupRegisters] backup number over 64!!!\n"));
+		err("[DramcBackupRegisters] backup number over 64!!!\n");
 		while (1);
 	}
 
@@ -2362,7 +2362,7 @@ void DramcBackupRegisters(DRAMC_CTX_T *p, U32 *backup_addr, U32 backup_num)
 	for (u4RegIdx = 0; u4RegIdx < backup_num; u4RegIdx++)
 	{
 		u4gpRegBackupVlaue[u4RegIdx] = u4IO32Read4B(backup_addr[u4RegIdx]);
-		//mcSHOW_DBG_MSG(("Backup Reg(0x%X) = 0x%X\n", backup_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]));
+		//msg("Backup Reg(0x%X) = 0x%X\n", backup_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]);
 	}
 }
 
@@ -2373,7 +2373,7 @@ void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num)
 #ifdef __ETT__
 	if (u1gpRegBackup == 0)
 	{
-		mcSHOW_ERR_MSG(("[DramcRestoreRegisters] Need to call backup first\n"));
+		err("[DramcRestoreRegisters] Need to call backup first\n");
 	}
 
 	u1gpRegBackup--;
@@ -2382,7 +2382,7 @@ void DramcRestoreRegisters(DRAMC_CTX_T *p, U32 *restore_addr, U32 restore_num)
 	for (u4RegIdx = 0; u4RegIdx < restore_num; u4RegIdx++)
 	{
 		vIO32Write4B(restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]);
-		//mcSHOW_DBG_MSG(("Restore Reg(0x%X) = 0x%X\n", restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]));
+		//msg("Restore Reg(0x%X) = 0x%X\n", restore_addr[u4RegIdx], u4gpRegBackupVlaue[u4RegIdx]);
 	}
 }
 
@@ -2410,14 +2410,14 @@ void DramcConfInfraReset(DRAMC_CTX_T *p)
 		vIO32WriteFldAlign_All(DDRPHY_MISC_CG_CTRL0, 0, MISC_CG_CTRL0_W_CHG_MEM);//disable memory clock change
 
 		// dramc conf reset
-		//mcSHOW_TIME_MSG(("Before infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148)));
+		//time_msg("Before infra reset, 0x10001148:%x\n", *(volatile unsigned *)(0x10001148));
 		*(volatile unsigned *)(0x10001140) = (0x1 << 15);
-		//mcSHOW_TIME_MSG(("After infra reset, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148)));
+		//time_msg("After infra reset, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148));
 		__asm__ __volatile__ ("dsb" : : : "memory");
 		mcDELAY_US(200);
-		//mcSHOW_TIME_MSG(("Before infra clear, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148)));
+		//time_msg("Before infra clear, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148));
 		*(volatile unsigned *)(0x10001144) = (0x1 << 15);
-		//mcSHOW_TIME_MSG(("After infra clear, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148)));
+		//time_msg("After infra clear, 0x10001148:%x\n",  *(volatile unsigned *)(0x10001148));
 
 		#if 0
 		mcDELAY_US(200);
@@ -2474,8 +2474,8 @@ U32 TimeProfileEnd(void)
 #if __ETT__
 	l_low_tick1 = GPT_GetTickCount(&l_high_tick1);
 
-	//mcSHOW_TIME_MSG(("Time0 %u %u\n", l_high_tick0, l_low_tick0));
-	//mcSHOW_TIME_MSG(("Time1 %u %u\n", l_high_tick1, l_low_tick1));
+	//time_msg("Time0 %u %u\n", l_high_tick0, l_low_tick0);
+	//time_msg("Time1 %u %u\n", l_high_tick1, l_low_tick1);
 	return ((l_low_tick1 - l_low_tick0) * 76) / 1000;
 #else
 	l_low_tick1 = get_timer(l_low_tick0);
diff --git a/src/vendorcode/mediatek/mt8192/include/dramc_common.h b/src/vendorcode/mediatek/mt8192/include/dramc_common.h
index 04d07a025c..599ebe935f 100644
--- a/src/vendorcode/mediatek/mt8192/include/dramc_common.h
+++ b/src/vendorcode/mediatek/mt8192/include/dramc_common.h
@@ -45,47 +45,49 @@
 /**********************************************/
 /* Priority of debug log                      */
 /*--------------------------------------------*/
-/* mcSHOW_DBG_MSG: High                       */
-/* mcSHOW_DBG_MSG2: Medium High               */
-/* mcSHOW_DBG_MSG3: Medium Low                */
-/* mcSHOW_DBG_MSG4: Low                       */
+/* msg: High                       */
+/* msg2: Medium High               */
+/* msg3: Medium Low                */
+/* msg4: Low                       */
 /**********************************************/
 
 #define CALIBRATION_LOG		1
 
 #if CALIBRATION_LOG
-#define mcSHOW_DBG_MSG(_x_)	{print _x_;}
-#define mcSHOW_DBG_MSG2(_x_)	//{print _x_;}
-#define mcSHOW_ERR_MSG(_x_) 	{print _x_;}
+#define msg(_x_...)	{ print(_x_); }
+#define msg2(_x_...)	// { print(_x_); }
+#define err(_x_...) 	{ print(_x_); }
 #else
-#define mcSHOW_DBG_MSG(_x_)
-#define mcSHOW_DBG_MSG2(_x_)
-#define mcSHOW_ERR_MSG(_x_)
+#define msg(_x_...)
+#define msg2(_x_...)
+#define err(_x_...)
 #endif
 
-#define mcSHOW_DBG_MSG3(_x_) // {print _x_;}
-#define mcSHOW_DBG_MSG4(_x_)
-#define mcSHOW_DBG_MSG5(_x_)
-#define mcSHOW_JV_LOG_MSG(_x_)
+#define info(_x_...) msg(_x_)
+
+#define msg3(_x_...) // { print(_x_); }
+#define msg4(_x_...)
+#define msg5(_x_...)
+#define jv_msg(_x_...)
 #if EYESCAN_LOG
-#define mcSHOW_EYESCAN_MSG(_x_) {print _x_;}
+#define eye_msg(_x_...) { print(_x_); }
 #else
-#define mcSHOW_EYESCAN_MSG(_x_) //{print _x_;}
+#define eye_msg(_x_...) //{ print(_x_); }
 #endif
-#define mcSHOW_DBG_MSG5(_x_)
-#define mcSHOW_TIME_MSG(_x_)
-#define mcDUMP_REG_MSG(_x_)
-#define mcFPRINTF(_x_)
+
+#define time_msg(_x_...)
+#define reg_msg(_x_...)
+#define mcFPRINTF(_x_...)
 
 #ifndef ARRAY_SIZE
 #define ARRAY_SIZE(x)    (sizeof (x) / sizeof (x[0]))
 #endif
 
 #define enter_function() \
-	({mcSHOW_DBG_MSG(("enter %s\n", __FUNCTION__));})
+	( { msg("enter %s\n", __FUNCTION__); } )
 
 #define exit_function() \
-	({mcSHOW_DBG_MSG(("exit %s\n", __FUNCTION__));})
+	( { msg("exit %s\n", __FUNCTION__); } )
 
 extern int dump_log;
 #endif   // _DRAMC_COMMON_H_
diff --git a/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h b/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h
index 5f48baeb5f..b1ec3ae9aa 100644
--- a/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h
+++ b/src/vendorcode/mediatek/mt8192/include/sv_c_data_traffic.h
@@ -8,7 +8,7 @@
 
 #define print_svarg(arg) \
 ({ \
-	mcSHOW_DBG_MSG((TOSTRING(arg) "=0x%x\n", psra->arg)); \
+	msg(TOSTRING(arg) "=0x%x\n", psra->arg); \
 })
 
 /*