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authorChris Wang <chris.wang@amd.corp-partner.google.com>2021-02-03 04:32:06 +0800
committerMartin Roth <martinroth@google.com>2021-02-05 23:36:25 +0000
commit68d68f1d7c7693f7e49634b6c2106d3c2630d4b0 (patch)
treefd5100feff6968735ad41f803c2d6d7397904fb5 /src/vendorcode/amd/fsp/picasso
parent4cecca49250e46375efbccf61e6085762c140c4c (diff)
soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust
add UPD for RV2 USB3 phy setting adjust. Note: it only for RV2 silicon and not available for RV/PCO. Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL -Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN -Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build/verify the valule will been apply on dirinboz Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/fsp/picasso')
-rw-r--r--src/vendorcode/amd/fsp/picasso/FspsUpd.h13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
index aac6fdbcfb..f931bf06e6 100644
--- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h
+++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h
@@ -12,6 +12,7 @@
#define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 8
#define FSPS_UPD_DDI_DESCRIPTOR_COUNT 4
#define FSPS_UPD_USB2_PORT_COUNT 6
+#define FSPS_UPD_RV2_USB3_PORT_COUNT 4
typedef struct __packed {
/** Offset 0x0020**/ uint32_t emmc0_mode;
@@ -54,7 +55,17 @@ typedef struct __packed {
/** Offset 0x0139**/ uint8_t pwron_varybl_to_blon;
/** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff;
/** Offset 0x013B**/ uint8_t min_allowed_bl_level;
- /** Offset 0x013C**/ uint8_t UnusedUpdSpace0[20];
+ /** Offset 0x013C**/ uint8_t usb_3_phy_enable;
+ /** Offset 0x013D**/ uint8_t usb_3_port_phy_tune[FSPS_UPD_RV2_USB3_PORT_COUNT][2];
+ /** Offset 0x0145**/ uint8_t usb_3_rx_vref_ctrl;
+ /** Offset 0x0146**/ uint8_t usb_3_rx_vref_ctrl_en;
+ /** Offset 0x0147**/ uint8_t usb_3_tx_vboost_lvl;
+ /** Offset 0x0148**/ uint8_t usb_3_tx_vboost_lvl_en;
+ /** Offset 0x0149**/ uint8_t usb_3_rx_vref_ctrl_x;
+ /** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x;
+ /** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x;
+ /** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x;
+ /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3];
/** Offset 0x0150**/ uint16_t UpdTerminator;
} FSP_S_CONFIG;