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authorPaul Menzel <paulepanter@users.sourceforge.net>2014-01-25 15:59:31 +0100
committerMartin Roth <martinroth@google.com>2016-01-07 17:40:45 +0100
commit2e0d9447db22183e2d3393d84e221e8bb1613d45 (patch)
treed481c26efa3b5501505f116226d747dd36d730a3 /src/vendorcode/amd/agesa/f12/Legacy
parentf8532b16bec1743b0528a215c71f67c8845e2a0c (diff)
src/vendorcode/amd: correct spelling of MTRR
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/4806 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Legacy')
-rw-r--r--src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
index bf8e6d206d..eac7c2a723 100644
--- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
@@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
- // Fixed MTTR region
+ // Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
- // Turn on MTTR enable bit and turn off modification bit
+ // Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
- // Variable MTTR region
+ // Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader);