AGESA: Add romstage timestamps

Experiments on f14 f15tn and 16kb suggest that TSC
counter value shifts at end of raminit. To account
for this all previously stored values in timestamp
table are also divided by 4.

Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

0 files changed, 0 insertions, 0 deletions